65816 Overview

Introduction

The Western Design Center W65C816 (aka 65C816, 65816, or just 816) is 16-bit upgrade to the 65c02. By default, it starts up in emulation mode, which is compatible with a WDC 65C02 without the extended Rockwell instructions. In emulation mode, all registers are 8 bits wide, the zero page is locked to $00xx, the stack is locked to $01xx, and the flags and interrupt vectors behave as expected for a 65c02. Note that all of the the additional 816 instructions are actually usable in this mode!

Switching to "native" mode, the S register becomes 16 bits wide, the A register can be switched between either 8 or 16 bits wide, X and Y (always together) can be switched between either 8 or 16 bits wide, and the zero page becomes a direct page which may be placed anywhere in the first 64k. Additionally, the K registers sets the bank used for code, and the B register sets the bank used for extended data transfers. Note however, that with the standard FPGA load, the upper 8-bits of all 24-bit addresses are treated by the hardware as if they were set to zero. Finally, interrupts vector to an entirely different set of vectors, making it possible for interrupts to function correctly in either mode.

Upgrading

The 65c02 in the F256 may be upgraded to a 65816 with the following caveats:

• You must use a 65C816SP part; slower models will not work.
• The 816 does not support the extended Rockwell 6502 instructions (BBS/BBR/SMB/RMB); these instructions must be avoided for software to maintain 816 compatibility. Software using these instructions will not run correctly on a 65816.

Programming

• The standard FPGA load ignores the upper 8-bits of all 24-bit transfers; you will still need to use the MMU to access more than 64k.
• If you are not booting to the stock MicroKernel, you will need to tell the FPGA that you have an 816 installed.

      ; If this is a 65816, switch pin 3 from an input
      ; (for PHI0-out) to a 1 output (for ABORTB-in).
        .cpu    "65816"
        clc
        xce
        bcc     +
        sec
        xce
        stz     $1
        lda     #$03
        sta     $d6b0
+      .cpu    "w65c02"  

• If you are experimenting with the F816e 24-bit 816 load for the Rev B Jr's FPGA, see the 24-bit wiki for more details: https://wiki.c256foenix.com/index.php?title=C256

Kernel Support

• The MicroKernel does not support the 816 running in native mode. You can still use the enhanced instructions in emulation mode, and you can temporarily switch to native mode while interrupts are disabled, but note that such software will not run correctly on standard 65c02 machines.
• The OpenFNXKernal endeavors to function correctly in both modes.

Historical Notes

Introduced in 1983, the W65C816 is an enhanced version of the WDC W65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU.

The 65C816 is a CPU option supported by the Foenix F256, that can be dropped-in, in place pf the default W65C02 processor supplied with the F256.

The "65" in the part's designation comes from its 65C02 compatibility mode, and the "816" signifies that the MPU has selectable 8-bit and 16-bit register sizes. In addition to the availability of 16-bit registers, the W65C816 processor itself extends potential memory addressing to 24-bits, supporting up to 16 megabytes of random-access memory. It has an enhanced instruction set and a 16-bit stack pointer, as well as several new control signals for improved system hardware management.

Despite allowing 24-bit addressing, a 65816 installed in a Foenix F256 still utilises the same 16-bit physical address space of the original W65C02 processor.

At reset, the W65C816 starts in "emulation mode", meaning it substantially behaves as a 65C02. In fact, a 65816 in default power-up "emulation mode" is cycle-accurate with the original MOS 6502 processor, whereas the W65C02 differs on some instructions.

User programs can then switch the W65C816 to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of backward compatibility with most 65C02 software.

However, unlike the DIP40 version of the W65C02, which is more-or-less a pin-compatible replacement for its NMOS ancestor (excepting mostly pin 1 - Vss / VPB), the DIP40 W65C816 is not directly pin-compatible with any other 6502 family MPU.

The W65C816 pin differences are mostly around the clock pins and some control pins. Despite this, the W65C816 can be a drop-in replacement for the W65C02 on the Foenix F256 series. No FPGA upgrade is necessary when in emulation mode (#).

(#) This point (noted from the main site F256K ordering page), needs more explanation by someone more knowledgable on F256 operation with a W65C816 processor installed.