Use the OPL3 YMF262: Difference between revisions

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(Created page with "== The YMF262 is inside the FPGA of some machines == The F256 machines, except the F256Jr., have in their Beatrix FPGA a YMF262 capable of Yamaha OPL3 that uses up to 36 operators. You can also use it in compatible OPL2 that uses a subset of up to 18 operators<br> {| class="wikitable" |+ !Register Name !Address !Description |- |OPL_ADDR_L |0xD580 |Register for addressing ports 0x000 to 0x0FF |- |OPL_DATA |0xD581 |Data register for all ports |- |OPL_ADDR_H |0xD582 |R...")
 
(new channel wide registers and operator wide registers, and the mapping for all 18 channels when using operator wide regs)
 
(2 intermediate revisions by the same user not shown)
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The F256 machines, except the F256Jr., have in their Beatrix FPGA a YMF262 capable of Yamaha OPL3 that uses up to 36 operators. You can also use it in compatible OPL2 that uses a subset of up to 18 operators<br>
The F256 machines, except the F256Jr., have in their Beatrix FPGA a YMF262 capable of Yamaha OPL3 that uses up to 36 operators. You can also use it in compatible OPL2 that uses a subset of up to 18 operators<br>


=== F256 registers for 6502, 65816, 6809(?) cores ===
{| class="wikitable"
{| class="wikitable"
|+
|+
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|Register for addressing ports 0x100 to 0x1FF
|Register for addressing ports 0x100 to 0x1FF
|}
|}
===== Usage: =====
When targetting a port in the 0x000 - 0x0FF range, send the port byte to 0xD580, then its data byte to 0x581.
When targetting a port in the 0x100 - 0x1FF range, send the port byte ''masked with 0x0FF to 0xD582,'' then its data byte to 0xD581''.''
Example 1: to start the chip using port 0x01, send 0x01 to 0xD580, then 0x01 to 0xD581.
Example 2: to enable OPL3 using port 0x105, send 0x05 to 0xD582, then 0x01 to 0xD581.


=== Chip wide ports ===
=== Chip wide ports ===
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| -
| -
| -
| -
| ChB
| 4-OP B-E
| ChA
| 4-OP A-D
| Ch9
| 4-OP 9-C
| Ch2
| 4-OP 2-5
| Ch1
| 4-OP 1-4
| Ch0
| 4-OP 0-3
|-
|-
| colspan="2" |
| colspan="2" |
Line 173: Line 183:
| Tre
| Tre
| Vib
| Vib
| Per
| Perc Mode
| BassDrum
| BassDrum
| SnareDrum
| SnareDrum
Line 181: Line 191:
|-
|-
| colspan="2" |  
| colspan="2" |  
| colspan="9" | B7 and B6 set = more present effect. <br>
| colspan="9" | B7 and B6 set = more present effect. <br>B5 being set enables these 4 default percussive instruments
When using B0-B4, key-on in channels 6,7,8 and their fnums have to be cleared! Their ADSR must be appropriate<br>
When using B0-B4, key-on in channels 6,7,8 and their fnums have to be cleared! Their ADSR must be appropriate<br>
This register is only used in OPL2 lower half, it does not affect higher half OPL3.
This register is only used in OPL2 lower half, it does not affect higher half OPL3.
Line 188: Line 198:


=== Channel wide ports ===
=== Channel wide ports ===
{| class="wikitable"
|+
!Port Name
!Port Address
!Description
!B7
!B6
!B5
!B4
!B3
!B2
!B1
!B0
|-
|Frequency Number (LO)
|0xA0
|The first 8 out of 10 bits of frequency value
| colspan="8" |Frequency Number (L)
|-
|
|
| colspan="9" |One only needs to generate 12 semi-tones once and use them over and over for western equal temperament music
{0x205, 0x223, 0x244, 0x267, 0x28B, 0x2B2, 0x2DB, 0x306, 0x334, 0x365, 0x399, 0x3CF}  this array also includes
the top 2 bits used in the next register base of 0xB0.
|-
|Key On - Freq Block - Freq Num (Hi)
|0xB0
|Last 2 out of 10 bits of frequency value.
| -
| -
|Key On
| colspan="3" |Freq Block
| colspan="2" |FNum (H)
|-
|
|
| colspan="9" |Key On toggles in the playing of the note on/off. Block kinda switches octaves
|-
|Feedback - Algorithm
|0xC0
|
|OutChD
|OutChB
|R
|L
| colspan="3" |Feedback
|Synth
|-
|
|
| colspan="9" |Digital audio outputs R = right speaker, L = left speaker, B = 3rd output, D = 4th output
Feedback: sends a portion of its output back to itself if set between value of 1-7
Synthesis types:
{| class="wikitable"
|+
!Op 1&2
!Op 3&4
!Type
|-
|0
|None
|FM
|-
|1
|None
|AM
|-
|0
|0
|FM-FM
|-
|1
|0
|AM-FM
|-
|0
|1
|FM-AM
|-
|1
|1
|AM-AM
|}
|}
=== Operator wide ports ===
{| class="wikitable"
|+
!Port Name
!Port Address
!Description
!B7
!B6
!B5
!B4
!B3
!B2
!B1
!B0
|-
|Various Effects
|0x20
|
|Tremolo
|Vibrato
|Sus
|KSR
| colspan="4" |Multiplication
|-
|
|
| colspan="9" |Tremolo and Vibrato turn the effects on and off
Sustain until key off
Enveloppe scaling KSR, when 1, higher notes are shorter than lower notes
Bits 0-3: Frequency Mutiplication, adds a multiplication coefficient to the note frequency
multi 0 is a factor of 0.5
multi 1 is 1
multi 2 is 2 and so on
|-
|KSL and output levels
|0x40
|
| colspan="2" |KSL 0-3
| colspan="6" |Output Level 0-32
|-
|
|
| colspan="9" |Key Scale Level is the attenuation of output level at higher pitch
KSL 0 : none KSL 1: 3dB/octave, KSL  2: 1.5 dB/octave, KSL 3: 6.0 dB/octave
Output level works in reverse: 0 is the loudest, 0x3F is the softest.
|-
!Port Name
!Port Address
!Description
!B7
!B6
!B5
!B4
!B3
!B2
!B1
!B0
|-
|Attack and Decay
|0x60
|
| colspan="4" |Attack 0x00 to 0x0F
| colspan="4" |Decay 0x00 to 0x0F
|-
|Sustain and Release
|0x80
|
| colspan="4" |Sustain 0x00 to 0x0F
| colspan="4" |Release 0x00 to 0x0F
|-
|Waveform select
|0xE0
|
|
|
|
|
|
| colspan="3" |Waveform
|-
|
|
| colspan="9" |Chip wide register 0x01's bit 5 must be set to 1 to enable all of the following


to be continued
Waveforms of 4-7 are only available with OPL3
{| class="wikitable"
|+
!Value
!Type
|-
|0
|Sine
|-
|1
|Half-sine
|-
|2
|Absolute value sine
|-
|3
|Pulse Sine
|-
|4
|Sine with even periods only
|-
|5
|Absolute sine with even periods only
|-
|6
|Square
|-
|7
|Derived Square
|}
|}


=== Operator wide ports ===
==== Accessing all the operators ====
In order to access all the operator's registers, you must apply an offset to all of the previous addresses from the above section, which were all relevant to operator 0.


to be continued
Here are a couple of examples to help visualize this:
{| class="wikitable"
|+
!
! colspan="18" |Operators of bank 0 (OPL2 and OPL3)
|-
!
! colspan="2" |Channel 1
! colspan="2" |Channel 2
! colspan="2" |Channel 3
! colspan="2" |Channel 4
! colspan="2" |Channel 5
! colspan="2" |Channel 6
! colspan="2" |Channel 7
! colspan="2" |Channel 8
! colspan="2" |Channel 9
|-
!Operators---->
!1
!4
!2
!5
!3
!6
!7
!10
!8
!11
!9
!12
!13
!16
!14
!17
!15
!18
|-
!Modulator or Carrier ---->
!M1
!C1
!M2
!C2
!M3
!C3
!M4
!C4
!M5
!C5
!M6
!C6
!M7
!C7
!M8
!C8
!M9
!C9
|-
|Register for Various Effects
|0x20
|0x23
|0x21
|0x24
|0x22
|0x25
|0x28
|0x2B
|0x29
|0x2C
|0x2A
|0x2D
|0x30
|0x33
|0x31
|0x34
|0x32
|0x35
|-
|Register for KSL and output levels
|0x40
|0x43
|0x41
|0x44
|0x42
|0x45
|0x48
|0x4B
|0x49
|0x4C
|0x4A
|0x4D
|0x50
|0x53
|0x51
|0x54
|0x52
|0x55
|}
For OPL3, these addresses for channels 10 to 18 are the same, but you need to send these registers to 0xD582 (instead of 0xD580), then the value to 0xD581.

Latest revision as of 22:24, 24 November 2025

The YMF262 is inside the FPGA of some machines

The F256 machines, except the F256Jr., have in their Beatrix FPGA a YMF262 capable of Yamaha OPL3 that uses up to 36 operators. You can also use it in compatible OPL2 that uses a subset of up to 18 operators

F256 registers for 6502, 65816, 6809(?) cores

Register Name Address Description
OPL_ADDR_L 0xD580 Register for addressing ports 0x000 to 0x0FF
OPL_DATA 0xD581 Data register for all ports
OPL_ADDR_H 0xD582 Register for addressing ports 0x100 to 0x1FF
Usage:

When targetting a port in the 0x000 - 0x0FF range, send the port byte to 0xD580, then its data byte to 0x581.

When targetting a port in the 0x100 - 0x1FF range, send the port byte masked with 0x0FF to 0xD582, then its data byte to 0xD581.

Example 1: to start the chip using port 0x01, send 0x01 to 0xD580, then 0x01 to 0xD581.

Example 2: to enable OPL3 using port 0x105, send 0x05 to 0xD582, then 0x01 to 0xD581.

Chip wide ports

Port Name Port Address Description B7 B6 B5 B4 B3 B2 B1 B0
Test Register / Waveform Select Enable 0x01 Must be used to "start the chip" Test Register Wave Select Enable Test Register
Set all Test Register bits to 0 to start the chip. B5 clear = all sine waves B5 set= enables wave choices in 0xE0-F5
Timer 1 Count 0x02 8bit timer with resolution of 80 us.
If overflow occurs, status register is set and preset value is loaded
Port Name Port Address Description B7 B6 B5 B4 B3 B2 B1 B0
Timer 2 Count 0x03 8bit timer with resolution of 320 us.
If overflow occurs, status register is set and preset value is loaded
IRQ-Reset/Mask/Start 0x04 Timer controls Reset T1Mask T2Mask - - - T2Start T1Start
B7 resets and IRQ flags status reg and ignore all others when this is set

B6 timer 1 mask. status reg is not affected in overflow
B5 timer 2 mask. same for timer2
B1 Timer 2 start. timer on/off
B0 Timer 1 start, same

Port Name Port Address Description B7 B6 B5 B4 B3 B2 B1 B0
Four-Operator Enable 0x104 Sets up four-operator channels - - 4-OP B-E 4-OP A-D 4-OP 9-C 4-OP 2-5 4-OP 1-4 4-OP 0-3
When fully set 0, 18 two-operator pairs are formed. When non-zero, four-operators are formed at specific locations

B5: channels 11-14 (decimal) are grouped
B4: channels 10-13
B3: channels 9-12
B2: channels 2-5
B1: channels 1-4
B0: channels 0-3

OPL3 Mode Enable 0x105 enables OPL3 extensions - - - - - - - Enable
set B0 to enable 36 operators, 4-OP synth, 8 waveforms, stereo output. When cleared, OPL2 is enabled.
Port Name Port Address Description B7 B6 B5 B4 B3 B2 B1 B0
Tremolo/Vibrato/Percussion 0xBD Bits 0-4 are treated as key-on/key-offs. Tre Vib Perc Mode BassDrum SnareDrum Tom-Tom Cymbal Hi-Hat
B7 and B6 set = more present effect.
B5 being set enables these 4 default percussive instruments

When using B0-B4, key-on in channels 6,7,8 and their fnums have to be cleared! Their ADSR must be appropriate
This register is only used in OPL2 lower half, it does not affect higher half OPL3.


Channel wide ports

Port Name Port Address Description B7 B6 B5 B4 B3 B2 B1 B0
Frequency Number (LO) 0xA0 The first 8 out of 10 bits of frequency value Frequency Number (L)
One only needs to generate 12 semi-tones once and use them over and over for western equal temperament music

{0x205, 0x223, 0x244, 0x267, 0x28B, 0x2B2, 0x2DB, 0x306, 0x334, 0x365, 0x399, 0x3CF} this array also includes the top 2 bits used in the next register base of 0xB0.

Key On - Freq Block - Freq Num (Hi) 0xB0 Last 2 out of 10 bits of frequency value. - - Key On Freq Block FNum (H)
Key On toggles in the playing of the note on/off. Block kinda switches octaves
Feedback - Algorithm 0xC0 OutChD OutChB R L Feedback Synth
Digital audio outputs R = right speaker, L = left speaker, B = 3rd output, D = 4th output

Feedback: sends a portion of its output back to itself if set between value of 1-7 Synthesis types:

Op 1&2 Op 3&4 Type
0 None FM
1 None AM
0 0 FM-FM
1 0 AM-FM
0 1 FM-AM
1 1 AM-AM

Operator wide ports

Port Name Port Address Description B7 B6 B5 B4 B3 B2 B1 B0
Various Effects 0x20 Tremolo Vibrato Sus KSR Multiplication
Tremolo and Vibrato turn the effects on and off

Sustain until key off Enveloppe scaling KSR, when 1, higher notes are shorter than lower notes Bits 0-3: Frequency Mutiplication, adds a multiplication coefficient to the note frequency multi 0 is a factor of 0.5 multi 1 is 1 multi 2 is 2 and so on

KSL and output levels 0x40 KSL 0-3 Output Level 0-32
Key Scale Level is the attenuation of output level at higher pitch

KSL 0 : none KSL 1: 3dB/octave, KSL 2: 1.5 dB/octave, KSL 3: 6.0 dB/octave Output level works in reverse: 0 is the loudest, 0x3F is the softest.

Port Name Port Address Description B7 B6 B5 B4 B3 B2 B1 B0
Attack and Decay 0x60 Attack 0x00 to 0x0F Decay 0x00 to 0x0F
Sustain and Release 0x80 Sustain 0x00 to 0x0F Release 0x00 to 0x0F
Waveform select 0xE0 Waveform
Chip wide register 0x01's bit 5 must be set to 1 to enable all of the following

Waveforms of 4-7 are only available with OPL3

Value Type
0 Sine
1 Half-sine
2 Absolute value sine
3 Pulse Sine
4 Sine with even periods only
5 Absolute sine with even periods only
6 Square
7 Derived Square

Accessing all the operators

In order to access all the operator's registers, you must apply an offset to all of the previous addresses from the above section, which were all relevant to operator 0.

Here are a couple of examples to help visualize this:

Operators of bank 0 (OPL2 and OPL3)
Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9
Operators----> 1 4 2 5 3 6 7 10 8 11 9 12 13 16 14 17 15 18
Modulator or Carrier ----> M1 C1 M2 C2 M3 C3 M4 C4 M5 C5 M6 C6 M7 C7 M8 C8 M9 C9
Register for Various Effects 0x20 0x23 0x21 0x24 0x22 0x25 0x28 0x2B 0x29 0x2C 0x2A 0x2D 0x30 0x33 0x31 0x34 0x32 0x35
Register for KSL and output levels 0x40 0x43 0x41 0x44 0x42 0x45 0x48 0x4B 0x49 0x4C 0x4A 0x4D 0x50 0x53 0x51 0x54 0x52 0x55

For OPL3, these addresses for channels 10 to 18 are the same, but you need to send these registers to 0xD582 (instead of 0xD580), then the value to 0xD581.