Memory Management: Difference between revisions

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The F256 line comes with 512 KB of RAM and 512 KB of flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the [[Expansion Port]].
== Overview ==
 
The F256 series comes with 512KB or 2MB of SRAM, and 512 KB of internal system flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the [[Expansion Port]].
=== Physical Memory Layout ===
 
The address bus is 21 bits wide, allowing a total of 2<sup>21</sup> = 2 MB to be addressed.
 
{| class="wikitable"
{| class="wikitable"
!Address!!Purpose
|+F256 Series Memory Capabilities
!Model
!Hardware CPU
!SRAM
!Flash
!Expansion Port
!DRAM
|-
|-
|$00:0000 - $07:FFFF||RAM
|F256Jr
|65C02
|512kB (512k×8)
|512kB
|256kB
|­—
|-
|-
|$08:0000 - $0F:FFFF||Flash
|F256K
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|-
|$10:0000 - $13:FFFF||Expansion Memory
|F256Jr2
|65816
|2MB (1M×16)
|512kB
|256kB
|—
|-
|-
|$14:0000 - $1F:FFFF||Reserved
|F256K2
|65816
|2MB (1M×16)
|512kB
|256kB
|128MB (not yet supported)
|}
|}
The 1st gen 65c02 systems have an 8-bit data bus and a 16-bit CPU address bus, with an MMU managing 8 × 8k banks to address 512kB RAM plus flash, expansion, and the IO pages.


=== Memory Management Unit (MMU) ===
The 2nd gen 2MB 65816 systems have 16-bit wide SRAMs, enabling higher bandwidth through the FPGA, even though the processor still has an 8-bit wide data bus. The same 64k address MMU with 512kB RAM configuration is used, but the Core2x FPGA core released in the summer of 2025 can enable 24 bit (16 MB) addressing and the full 2MB of SRAM both flat & banked.


While the address bus is generally 21 bits wide, the CPU address bus of the 65c02 and the FNX6809 is only 16 bits wide. Even though the 65816 does have a 24 bit wide address bus, it is currently not used in the classic 6502 MMU core. However, this is now possible with the extended memory map of the 2x speed 65816. These changes have been added in the summer of 2025 and are marked in <u>''italics and underlined''</u> in the following tables.
A FPGA-based 6809 CPU can be optionally run on all F256 models which will also use this same MMU, and disable the hardware CPU. A 68k FPGA-based processor core is also coming, which should use flat memory addressing only.
 
To allow the addressing of the whole address space, 4 Memory Management Units (MMU) are provided, that translate the CPU logical address space to physical addresses.
 
To achieve this, each MMU has 8 <em>slots</em>, each representing an 8 KB block of the CPU addressable memory space.
 
The physical address space is also divided into 8 KB blocks, dividing the available 2 MB into 256 blocks.
 
To <em>map</em> a block of physical addresses into CPU address space, the block number is written into the according slot register of the MMU.


'''NOTE:''' Changes associated with Core2x will be in <u>''italics and underlined''</u> throughout this page.
{| class="wikitable"
{| class="wikitable"
!Slot!!CPU Address Space!!Slot Register Address
|+Memory Mapping
!MMU 8kB Block Number
!24-Bit Address!!Purpose
!24-bit Enable Flag
|-
|-
|0||$0000 - $1FFF|| $0008
|$00 - $3F
|$00:0000 - $07:FFFF||512K SRAM Default RAM (Page 0)
|
|-
|$40 - $7F
|$08:0000 - $0F:FFFF||512K System Flash
|<u>''MOVE_FLASH''</u>
|-
|-
|1||$2000 - $3FFF|| $0009
|$80 - $9F
|$10:0000 - $13:FFFF||256K Cartridge
|<u>''MOVE_FLASH''</u>
|-
|-
|2||$4000 - $5FFF|| $000A
|$A0 - $FF
|$14:0000 - $1F:FFFF||Reserved
|
|-
|-
|3||$6000 - $7FFF|| $000B
|<u>''$100 - $13F''</u>
|$20:0000 - $27:FFFF
|<u>''512K SRAM Page 1''</u>
|<u>''SRAM_EN''</u>
|-
|-
|4||$8000 - $9FFF|| $000C
|<u>''$200 - $23F''</u>
|$40:0000 - $47:FFFF
|<u>''512K SRAM Page 2''</u>
|<u>''SRAM_EN''</u>
|-
|-
|5||$A000 - $BFFF|| $000D
|<u>''$300 - $33F''</u>
|$60:0000 - $67:FFFF
|<u>''512K SRAM Page 3''</u>
|<u>''SRAM_EN''</u>
|-
|-
|6||$C000 - $DFFF|| $000E
|IO_PAGE 0-3
|$F0:0000 - $F0:7FFF
|IO Pages
|<u>''MOVE_IO''</u>
|-
|-
|7||$E000 - $FFFF|| $000F
|<u>''IO_PAGE 4-5''</u>
|$F0:8000 - $F0:BFFF
|<u>''IO Pages''</u>
|<u>''MOVE_IO''</u>
|}
|}
Note that the SRAM pages 1-3 are '''not''' contiguous, but aligned to 1MB starting addresses.


Only one MMU is active at any one time. To select the active MMU, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.
== Memory Management Unit (MMU) ==
While the address bus is generally 21 bits wide, the CPU address bus of the 65c02 and the FNX6809 is only 16 bits wide. The 65816 defaults to a 64kB MMU mapped configuration as well, though the Core2x FPGA core enables the flat 24-bit address bus.


Editing of MMUs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which set of MMU registers is to be edited, while bit 7 has to be set to 1 to enable editing.
The MMU splits the 64kB address space into 8 visible slots of 8kB each. A theoretical max of 256 selectable 8kB banks yields a 2MB address space, which maps 512kB RAM, flash, and expansion. IO pages have their own space of numbered banks that overlay one fixed slot ($C000-$DFFF). The Core2x MMU expands the bank numbers to 10 bits, for 8MB of address space that can encompass the rest of the 2MB RAM.
When editing is enable, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
 
There are 4 separate sets of MMU configurations called MLUT 0-3 (Memory Lookup Tables), for easy switching between well-known (including kernel vs user) memory mapping states. Each MLUT holds 8 bank selections, one for each 8kB memory slot respectively. IO mapping is optional, independent of MLUT selection, and overrides slot 6 at $C000.
 
Only one MLUT is active at any one time. To select the active MLUT, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.
 
Editing of MLUTs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which MLUT to be edited, independent of which MLUT is active. Bit 7 has to be set to 1 to enable editing. When editing is enabled, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
{| class="wikitable"
{| class="wikitable"
|+MMU Registers
|+Static MMU Registers
!Address
!Address
!R/W
!R/W
Line 67: Line 118:
!0
!0
|-
|-
|0x0000
|$0000
|RW
|RW
|MMU_MEM_CTRL
|MMU_MEM_CTRL
Line 77: Line 128:
| colspan="2" |ACT_LUT
| colspan="2" |ACT_LUT
|-
|-
|0x0001
|$0001
|RW
|RW
|MMU_IO_CTRL
|MMU_IO_CTRL
Line 88: Line 139:
| colspan="2" |IO_PAGE
| colspan="2" |IO_PAGE
|}
|}
'''ACT_LUT''' these two bits specify which MLUT (0–3) is used to translate CPU bus address to system
{| class="wikitable"
 
|+MLUT Slot Editing Registers (only visible with EDIT_EN enabled)
bus addresses.
!Address
 
!R/W
'''EDIT_EN''' if set (1), this bit allows a MLUT to be edited by the program, and memory addresses
!MLUT Slot Address
 
!7
0x0008–0x0010 will be used by the MLUT being edited. If clear (0), those memory locations
!6
 
!5
will be standard memory locations and will be mapped like the rest of bank 0.
!4
 
!3
'''EDIT_LUT''' if '''EDIT_EN''' is set, these two bits will specify which MLUT (0 - 3) is being edited and
!2
 
!1
will appear in memory addresses 0x0008–0x0010.
!0
|-
|''<u>$0002</u>''
|
|
| colspan="2" |''<u>Slot 3, bits 8-9</u>''
| colspan="2" |''<u>Slot 2, bits 8-9</u>''
| colspan="2" |''<u>Slot 1, bits 8-9</u>''
| colspan="2" |''<u>Slot 0, bits 8-9</u>''
|-
|''<u>$0003</u>''
|
|
| colspan="2" |''<u>Slot 7, bits 8-9</u>''
| colspan="2" |''<u>Slot 6, bits 8-9</u>''
| colspan="2" |''<u>Slot 5, bits 8-9</u>''
| colspan="2" |''<u>Slot 4, bits 8-9</u>''
|-
|$0008
|
|$0000 - $1FFF
| colspan="8" |Edit MLUT slot 0, bits 0-7
|-
|$0009
|
|$2000 - $3FFF
| colspan="8" |Edit MLUT slot 1, bits 0-7
|-
|$000A
|
|$4000 - $5FFF
| colspan="8" |Edit MLUT slot 2, bits 0-7
|-
|$000B
|
|$6000 - $7FFF
| colspan="8" |Edit MLUT slot 3, bits 0-7
|-
|$000C
|
|$8000 - $9FFF
| colspan="8" |Edit MLUT slot 4, bits 0-7
|-
|$000D
|
|$A000 - $BFFF
| colspan="8" |Edit MLUT slot 5, bits 0-7
|-
|$000E
|
|$C000 - $DFFF
| colspan="8" |Edit MLUT slot 6, bits 0-7
|-
|$000F
|
|$E000 - $FFFF
| colspan="8" |Edit MLUT slot 7, bits 0-7
|}
'''ACT_LUT''': These two bits specify which MLUT (0–3) is used to translate CPU bus address to system bus addresses.


''<u>'''SRAM_EN'''</u>'' (2x speed 65816 core <u>only</u>) enables access to the SRAM in extended mode (24 bit addresses)
'''EDIT_LUT''': Selects which MLUT (0-3) will be edited.


'''EDIT_EN''': If set (1), this bit enables MLUT editing, and memory addresses $0008–$000F (<u>''and $0002-$0003''</u>) will be used to edit the selected '''EDIT_LUT'''. If clear (0), those memory locations will be standard memory locations and will be mapped like the rest of slot 0.


'''IO_DISABLE''' if set (1), bank 6 is mapped like any other memory bank. If clear (0), bank 6 is
'''IO_PAGE''': Selects which IO page (0-3) is mapped to slot 6, when not disabled with '''IO_DISABLE'''.


mapped to I/O memory.
'''IO_DISABLE''': If set (1), slot 6 ($C000-$DFFF) is mapped through the active MLUT as normal. If clear (0), slot 6 is mapped to the selected '''IO_PAGE'''.


'''IO_PAGE''' if '''IO_DISABLE''' is clear, these two bits specify which bank of I/O memory (0 - 3) is
Note that writing a simple page number to register $0001 easily selects that IO page (including 0) to be visible, although there are also other Core2x entries now as well.


mapped to bank 6.
==== Core2x MMU Registers ====
''<u>'''SRAM_EN'''</u>'': Enables access to the SRAM pages 1-3 in 24-bit addresses 20:0000, 40:0000, and 60:0000, respectively.


<u>'''''IO_PAGE_EXT'''''</u> (2x <u>only</u>)allows to access more io pages (4 and 5)
<u>'''''IO_PAGE_EXT'''''</u>: Bit 2 of the total IO page number, enabling pages 4 and 5.


<u>'''''MOVE_IO'''''</u> (2x <u>only</u>) Moves decoding of IO Devices to High-Memory
<u>'''''MOVE_IO'''''</u>: Moves IO pages from MMU access to 24-bit address F0:0000.


<u>'''''MOVE_FLASH'''''</u> (2x <u>only</u>) Moves decoding of Flash/Cart to High-Memory
<u>'''''MOVE_FLASH'''''</u>: Moves Flash & Cart addressing from MMU access to 24-bit address 08:0000.


<u>'''''SPR_SEL'''''</u> (2x <u>only</u>) Sprite Block Select - 0: Sprite 0-63, 1: Sprite 64-127
<u>'''''SPR_SEL'''''</u>: Select current Sprite Block in IO Page 0. 0 = Sprite 0-63, 1 = Sprite 64-127.
{| class="wikitable"
{| class="wikitable"
|+I/O Banks
|+I/O Pages
!I/O Bank
!I/O Page
!B3
!B3
!B1
!B1
!B0
!B0
!MOVE_IO Address
!Purpose
!Purpose
|-
|-
Line 132: Line 244:
|0
|0
|0
|0
|<u>''$F0:0000 - $F0:1FFF''</u>
|Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
|Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
|-
|-
Line 138: Line 251:
|0
|0
|1
|1
|<u>''$F0:2000 - $F0:3FFF''</u>
|Text display font memory and graphic color MLUTs 0,1,2,3
|Text display font memory and graphic color MLUTs 0,1,2,3
|-
|-
Line 144: Line 258:
|1
|1
|0
|0
|<u>''$F0:4000 - $F0:5FFF''</u>
|Text display character matrix
|Text display character matrix
|-
|-
Line 150: Line 265:
|1
|1
|1
|1
|<u>''$F0:6000 - $F0:7FFF''</u>
|Text display color matrix
|Text display color matrix
|-
|-
Line 156: Line 272:
|<u>''0''</u>
|<u>''0''</u>
|<u>''0''</u>
|<u>''0''</u>
|<u>''$F0:8000 - $F0:9FFF''</u>
|<u>''Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1''</u>
|<u>''Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1''</u>
|-
|-
Line 162: Line 279:
|<u>''0''</u>
|<u>''0''</u>
|<u>''1''</u>
|<u>''1''</u>
|<u>''$F0:A000 - $F0:BFFF''</u>
|<u>''Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16''</u>
|<u>''Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16''</u>
|-
|<u>''6''</u>
|<u>''1''</u>
|<u>''1''</u>
|<u>''0''</u>
|<u>''unused''</u>
|-
|<u>''7''</u>
|<u>''1''</u>
|<u>''1''</u>
|<u>''1''</u>
|<u>''unused''</u>
|}
|}


=== Memory Block Tables ===
== Memory Block Tables ==
Overview of the block tables, including the new RAM locations addressed by the 2x speed 65816 extended map core:
{| class="wikitable"
|+Address Decoding Overview
!Range
!Description
|-
|$00_0000 to $07_FFFF
|512K SRAM Default RAM (Page 0)
|-
|$08_0000 to $0F_0000
|512K FLASH
|-
|$10_0000 to $13_FFFF
|256K Cartridge
|-
|$14_000 to $1F_FFFF
|768K Nothing Here
|-
|$20_000 to $27_FFFF
|<u>''512K SRAM Page 1''</u>
|-
|$40_000 to $47_FFFF
|<u>''512K SRAM Page 2''</u>
|-
|$60_000 to $67_FFFF
|<u>''512K SRAM Page 3''</u>
|}
The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.
The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.


Line 357: Line 436:
|}
|}


For 2x speed extended map 65816 core:
For Core2x extended map 65816 core:
{| class="wikitable" style="border: none; background: none;"
{| class="wikitable" style="border: none; background: none;"
! colspan=2 scope=col| <u>''512K SRAM Page 1''</u>
! colspan=2 scope=col| <u>''512K SRAM Page 1''</u>

Latest revision as of 19:13, 6 October 2025

Overview

The F256 series comes with 512KB or 2MB of SRAM, and 512 KB of internal system flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the Expansion Port.

F256 Series Memory Capabilities
Model Hardware CPU SRAM Flash Expansion Port DRAM
F256Jr 65C02 512kB (512k×8) 512kB 256kB ­—
F256K 65C02 512kB (512k×8) 512kB 256kB —
F256Jr2 65816 2MB (1M×16) 512kB 256kB —
F256K2 65816 2MB (1M×16) 512kB 256kB 128MB (not yet supported)

The 1st gen 65c02 systems have an 8-bit data bus and a 16-bit CPU address bus, with an MMU managing 8 × 8k banks to address 512kB RAM plus flash, expansion, and the IO pages.

The 2nd gen 2MB 65816 systems have 16-bit wide SRAMs, enabling higher bandwidth through the FPGA, even though the processor still has an 8-bit wide data bus. The same 64k address MMU with 512kB RAM configuration is used, but the Core2x FPGA core released in the summer of 2025 can enable 24 bit (16 MB) addressing and the full 2MB of SRAM both flat & banked.

A FPGA-based 6809 CPU can be optionally run on all F256 models which will also use this same MMU, and disable the hardware CPU. A 68k FPGA-based processor core is also coming, which should use flat memory addressing only.

NOTE: Changes associated with Core2x will be in italics and underlined throughout this page.

Memory Mapping
MMU 8kB Block Number 24-Bit Address Purpose 24-bit Enable Flag
$00 - $3F $00:0000 - $07:FFFF 512K SRAM Default RAM (Page 0)
$40 - $7F $08:0000 - $0F:FFFF 512K System Flash MOVE_FLASH
$80 - $9F $10:0000 - $13:FFFF 256K Cartridge MOVE_FLASH
$A0 - $FF $14:0000 - $1F:FFFF Reserved
$100 - $13F $20:0000 - $27:FFFF 512K SRAM Page 1 SRAM_EN
$200 - $23F $40:0000 - $47:FFFF 512K SRAM Page 2 SRAM_EN
$300 - $33F $60:0000 - $67:FFFF 512K SRAM Page 3 SRAM_EN
IO_PAGE 0-3 $F0:0000 - $F0:7FFF IO Pages MOVE_IO
IO_PAGE 4-5 $F0:8000 - $F0:BFFF IO Pages MOVE_IO

Note that the SRAM pages 1-3 are not contiguous, but aligned to 1MB starting addresses.

Memory Management Unit (MMU)

While the address bus is generally 21 bits wide, the CPU address bus of the 65c02 and the FNX6809 is only 16 bits wide. The 65816 defaults to a 64kB MMU mapped configuration as well, though the Core2x FPGA core enables the flat 24-bit address bus.

The MMU splits the 64kB address space into 8 visible slots of 8kB each. A theoretical max of 256 selectable 8kB banks yields a 2MB address space, which maps 512kB RAM, flash, and expansion. IO pages have their own space of numbered banks that overlay one fixed slot ($C000-$DFFF). The Core2x MMU expands the bank numbers to 10 bits, for 8MB of address space that can encompass the rest of the 2MB RAM.

There are 4 separate sets of MMU configurations called MLUT 0-3 (Memory Lookup Tables), for easy switching between well-known (including kernel vs user) memory mapping states. Each MLUT holds 8 bank selections, one for each 8kB memory slot respectively. IO mapping is optional, independent of MLUT selection, and overrides slot 6 at $C000.

Only one MLUT is active at any one time. To select the active MLUT, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.

Editing of MLUTs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which MLUT to be edited, independent of which MLUT is active. Bit 7 has to be set to 1 to enable editing. When editing is enabled, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.

Static MMU Registers
Address R/W Name 7 6 5 4 3 2 1 0
$0000 RW MMU_MEM_CTRL EDIT_EN - EDIT_LUT SRAM_EN - ACT_LUT
$0001 RW MMU_IO_CTRL - SPR_SEL MOVE_FLASH MOVE_IO IO_PAGE_EXT IO_DISABLE IO_PAGE
MLUT Slot Editing Registers (only visible with EDIT_EN enabled)
Address R/W MLUT Slot Address 7 6 5 4 3 2 1 0
$0002 Slot 3, bits 8-9 Slot 2, bits 8-9 Slot 1, bits 8-9 Slot 0, bits 8-9
$0003 Slot 7, bits 8-9 Slot 6, bits 8-9 Slot 5, bits 8-9 Slot 4, bits 8-9
$0008 $0000 - $1FFF Edit MLUT slot 0, bits 0-7
$0009 $2000 - $3FFF Edit MLUT slot 1, bits 0-7
$000A $4000 - $5FFF Edit MLUT slot 2, bits 0-7
$000B $6000 - $7FFF Edit MLUT slot 3, bits 0-7
$000C $8000 - $9FFF Edit MLUT slot 4, bits 0-7
$000D $A000 - $BFFF Edit MLUT slot 5, bits 0-7
$000E $C000 - $DFFF Edit MLUT slot 6, bits 0-7
$000F $E000 - $FFFF Edit MLUT slot 7, bits 0-7

ACT_LUT: These two bits specify which MLUT (0–3) is used to translate CPU bus address to system bus addresses.

EDIT_LUT: Selects which MLUT (0-3) will be edited.

EDIT_EN: If set (1), this bit enables MLUT editing, and memory addresses $0008–$000F (and $0002-$0003) will be used to edit the selected EDIT_LUT. If clear (0), those memory locations will be standard memory locations and will be mapped like the rest of slot 0.

IO_PAGE: Selects which IO page (0-3) is mapped to slot 6, when not disabled with IO_DISABLE.

IO_DISABLE: If set (1), slot 6 ($C000-$DFFF) is mapped through the active MLUT as normal. If clear (0), slot 6 is mapped to the selected IO_PAGE.

Note that writing a simple page number to register $0001 easily selects that IO page (including 0) to be visible, although there are also other Core2x entries now as well.

Core2x MMU Registers

SRAM_EN: Enables access to the SRAM pages 1-3 in 24-bit addresses 20:0000, 40:0000, and 60:0000, respectively.

IO_PAGE_EXT: Bit 2 of the total IO page number, enabling pages 4 and 5.

MOVE_IO: Moves IO pages from MMU access to 24-bit address F0:0000.

MOVE_FLASH: Moves Flash & Cart addressing from MMU access to 24-bit address 08:0000.

SPR_SEL: Select current Sprite Block in IO Page 0. 0 = Sprite 0-63, 1 = Sprite 64-127.

I/O Pages
I/O Page B3 B1 B0 MOVE_IO Address Purpose
0 0 0 0 $F0:0000 - $F0:1FFF Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
1 0 0 1 $F0:2000 - $F0:3FFF Text display font memory and graphic color MLUTs 0,1,2,3
2 0 1 0 $F0:4000 - $F0:5FFF Text display character matrix
3 0 1 1 $F0:6000 - $F0:7FFF Text display color matrix
4 1 0 0 $F0:8000 - $F0:9FFF Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1
5 1 0 1 $F0:A000 - $F0:BFFF Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16

Memory Block Tables

The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.

RAM Flash Expansion
Block Number Physical Address Block Number Physical Address Block Number Physical Address
$00 $00:0000 - $00:1FFF $40 $08:0000 - $08:1FFF $80 $10:0000 - $10:1FFF
$01 $00:2000 - $00:3FFF $41 $08:2000 - $08:3FFF $81 $10:2000 - $10:3FFF
$02 $00:4000 - $00:5FFF $42 $08:4000 - $08:5FFF $82 $10:4000 - $10:5FFF
$03 $00:6000 - $00:7FFF $43 $08:6000 - $08:7FFF $83 $10:6000 - $10:7FFF
$04 $00:8000 - $00:9FFF $44 $08:8000 - $08:9FFF $84 $10:8000 - $10:9FFF
$05 $00:A000 - $00:BFFF $45 $08:A000 - $08:BFFF $85 $10:A000 - $10:BFFF
$06 $00:C000 - $00:DFFF $46 $08:C000 - $08:DFFF $86 $10:C000 - $10:DFFF
$07 $00:E000 - $00:FFFF $47 $08:E000 - $08:FFFF $87 $10:E000 - $10:FFFF
$08 $01:0000 - $01:1FFF $48 $09:0000 - $09:1FFF $88 $11:0000 - $11:1FFF
$09 $01:2000 - $01:3FFF $49 $09:2000 - $09:3FFF $89 $11:2000 - $11:3FFF
$0A $01:4000 - $01:5FFF $4A $09:4000 - $09:5FFF $8A $11:4000 - $11:5FFF
$0B $01:6000 - $01:7FFF $4B $09:6000 - $09:7FFF $8B $11:6000 - $11:7FFF
$0C $01:8000 - $01:9FFF $4C $09:8000 - $09:9FFF $8C $11:8000 - $11:9FFF
$0D $01:A000 - $01:BFFF $4D $09:A000 - $09:BFFF $8D $11:A000 - $11:BFFF
$0E $01:C000 - $01:DFFF $4E $09:C000 - $09:DFFF $8E $11:C000 - $11:DFFF
$0F $01:E000 - $01:FFFF $4F $09:E000 - $09:FFFF $8F $11:E000 - $11:FFFF
$10 $02:0000 - $02:1FFF $50 $0A:0000 - $0A:1FFF $90 $12:0000 - $12:1FFF
$11 $02:2000 - $02:3FFF $51 $0A:2000 - $0A:3FFF $91 $12:2000 - $12:3FFF
$12 $02:4000 - $02:5FFF $52 $0A:4000 - $0A:5FFF $92 $12:4000 - $12:5FFF
$13 $02:6000 - $02:7FFF $53 $0A:6000 - $0A:7FFF $93 $12:6000 - $12:7FFF
$14 $02:8000 - $02:9FFF $54 $0A:8000 - $0A:9FFF $94 $12:8000 - $12:9FFF
$15 $02:A000 - $02:BFFF $55 $0A:A000 - $0A:BFFF $95 $12:A000 - $12:BFFF
$16 $02:C000 - $02:DFFF $56 $0A:C000 - $0A:DFFF $96 $12:C000 - $12:DFFF
$17 $02:E000 - $02:FFFF $57 $0A:E000 - $0A:FFFF $97 $12:E000 - $12:FFFF
$18 $03:0000 - $03:1FFF $58 $0B:0000 - $0B:1FFF $98 $13:0000 - $13:1FFF
$19 $03:2000 - $03:3FFF $59 $0B:2000 - $0B:3FFF $99 $13:2000 - $13:3FFF
$1A $03:4000 - $03:5FFF $5A $0B:4000 - $0B:5FFF $9A $13:4000 - $13:5FFF
$1B $03:6000 - $03:7FFF $5B $0B:6000 - $0B:7FFF $9B $13:6000 - $13:7FFF
$1C $03:8000 - $03:9FFF $5C $0B:8000 - $0B:9FFF $9C $13:8000 - $13:9FFF
$1D $03:A000 - $03:BFFF $5D $0B:A000 - $0B:BFFF $9D $13:A000 - $13:BFFF
$1E $03:C000 - $03:DFFF $5E $0B:C000 - $0B:DFFF $9E $13:C000 - $13:DFFF
$1F $03:E000 - $03:FFFF $5F $0B:E000 - $0B:FFFF $9F $13:E000 - $13:FFFF
$20 $04:0000 - $04:1FFF $60 $0C:0000 - $0C:1FFF
$21 $04:2000 - $04:3FFF $61 $0C:2000 - $0C:3FFF
$22 $04:4000 - $04:5FFF $62 $0C:4000 - $0C:5FFF
$23 $04:6000 - $04:7FFF $63 $0C:6000 - $0C:7FFF
$24 $04:8000 - $04:9FFF $64 $0C:8000 - $0C:9FFF
$25 $04:A000 - $04:BFFF $65 $0C:A000 - $0C:BFFF
$26 $04:C000 - $04:DFFF $66 $0C:C000 - $0C:DFFF
$27 $04:E000 - $04:FFFF $67 $0C:E000 - $0C:FFFF
$28 $05:0000 - $05:1FFF $68 $0D:0000 - $0D:1FFF
$29 $05:2000 - $05:3FFF $69 $0D:2000 - $0D:3FFF
$2A $05:4000 - $05:5FFF $6A $0D:4000 - $0D:5FFF
$2B $05:6000 - $05:7FFF $6B $0D:6000 - $0D:7FFF
$2C $05:8000 - $05:9FFF $6C $0D:8000 - $0D:9FFF
$2D $05:A000 - $05:BFFF $6D $0D:A000 - $0D:BFFF
$2E $05:C000 - $05:DFFF $6E $0D:C000 - $0D:DFFF
$2F $05:E000 - $05:FFFF $6F $0D:E000 - $0D:FFFF
$30 $06:0000 - $06:1FFF $70 $0E:0000 - $0E:1FFF
$31 $06:2000 - $06:3FFF $71 $0E:2000 - $0E:3FFF
$32 $06:4000 - $06:5FFF $72 $0E:4000 - $0E:5FFF
$33 $06:6000 - $06:7FFF $73 $0E:6000 - $0E:7FFF
$34 $06:8000 - $06:9FFF $74 $0E:8000 - $0E:9FFF
$35 $06:A000 - $06:BFFF $75 $0E:A000 - $0E:BFFF
$36 $06:C000 - $06:DFFF $76 $0E:C000 - $0E:DFFF
$37 $06:E000 - $06:FFFF $77 $0E:E000 - $0E:FFFF
$38 $07:0000 - $07:1FFF $78 $0F:0000 - $0F:1FFF
$39 $07:2000 - $07:3FFF $79 $0F:2000 - $0F:3FFF
$3A $07:4000 - $07:5FFF $7A $0F:4000 - $0F:5FFF
$3B $07:6000 - $07:7FFF $7B $0F:6000 - $0F:7FFF
$3C $07:8000 - $07:9FFF $7C $0F:8000 - $0F:9FFF
$3D $07:A000 - $07:BFFF $7D $0F:A000 - $0F:BFFF
$3E $07:C000 - $07:DFFF $7E $0F:C000 - $0F:DFFF
$3F $07:E000 - $07:FFFF $7F $0F:E000 - $0F:FFFF

For Core2x extended map 65816 core:

512K SRAM Page 1 512K SRAM Page 2 512K SRAM Page 3
Block Number Physical Address Block Number Physical Address Block Number Physical Address
$100 $20:0000 - $20:1FFF $200 $40:0000 - $40:1FFF $300 $60:0000 - $60:1FFF
$101 $20:2000 - $20:3FFF $201 $40:2000 - $40:3FFF $301 $60:2000 - $60:3FFF
$102 $20:4000 - $20:5FFF $202 $40:4000 - $40:5FFF $302 $60:4000 - $60:5FFF
$103 $20:6000 - $20:7FFF $203 $40:6000 - $40:7FFF $303 $60:6000 - $60:7FFF
$104 $20:8000 - $20:9FFF $204 $40:8000 - $40:9FFF $304 $60:8000 - $60:9FFF
$105 $20:A000 - $20:BFFF $205 $40:A000 - $40:BFFF $305 $60:A000 - $60:BFFF
$106 $20:C000 - $20:DFFF $206 $40:C000 - $40:DFFF $306 $60:C000 - $60:DFFF
$107 $20:E000 - $20:FFFF $207 $40:E000 - $40:FFFF $307 $60:E000 - $60:FFFF
$108 $21:0000 - $21:1FFF $208 $41:0000 - $41:1FFF $308 $61:0000 - $61:1FFF
$109 $21:2000 - $21:3FFF $209 $41:2000 - $41:3FFF $309 $61:2000 - $61:3FFF
$10A $21:4000 - $21:5FFF $20A $41:4000 - $41:5FFF $30A $61:4000 - $61:5FFF
$10B $21:6000 - $21:7FFF $20B $41:6000 - $41:7FFF $30B $61:6000 - $61:7FFF
$10C $21:8000 - $21:9FFF $20C $41:8000 - $41:9FFF $30C $61:8000 - $61:9FFF
$10D $21:A000 - $21:BFFF $20D $41:A000 - $41:BFFF $30D $61:A000 - $61:BFFF
$10E $21:C000 - $21:DFFF $20E $41:C000 - $41:DFFF $30E $61:C000 - $61:DFFF
$10F $21:E000 - $21:FFFF $20F $41:E000 - $41:FFFF $30F $61:E000 - $61:FFFF
$110 $22:0000 - $22:1FFF $210 $42:0000 - $42:1FFF $310 $62:0000 - $62:1FFF
$111 $22:2000 - $22:3FFF $211 $42:2000 - $42:3FFF $311 $62:2000 - $62:3FFF
$112 $22:4000 - $22:5FFF $212 $42:4000 - $42:5FFF $312 $62:4000 - $62:5FFF
$113 $22:6000 - $22:7FFF $213 $42:6000 - $42:7FFF $313 $62:6000 - $62:7FFF
$114 $22:8000 - $22:9FFF $214 $42:8000 - $42:9FFF $314 $62:8000 - $62:9FFF
$115 $22:A000 - $22:BFFF $215 $42:A000 - $42:BFFF $315 $62:A000 - $62:BFFF
$116 $22:C000 - $22:DFFF $216 $42:C000 - $42:DFFF $316 $62:C000 - $62:DFFF
$117 $22:E000 - $22:FFFF $217 $42:E000 - $42:FFFF $317 $62:E000 - $62:FFFF
$118 $23:0000 - $23:1FFF $218 $43:0000 - $43:1FFF $318 $63:0000 - $63:1FFF
$119 $23:2000 - $23:3FFF $219 $43:2000 - $43:3FFF $319 $63:2000 - $63:3FFF
$11A $23:4000 - $23:5FFF $21A $43:4000 - $43:5FFF $31A $63:4000 - $63:5FFF
$11B $23:6000 - $23:7FFF $21B $43:6000 - $43:7FFF $31B $63:6000 - $63:7FFF
$11C $23:8000 - $23:9FFF $21C $43:8000 - $43:9FFF $31C $63:8000 - $63:9FFF
$11D $23:A000 - $23:BFFF $21D $43:A000 - $43:BFFF $31D $63:A000 - $63:BFFF
$11E $23:C000 - $23:DFFF $21E $43:C000 - $43:DFFF $31E $63:C000 - $63:DFFF
$11F $23:E000 - $23:FFFF $21F $43:E000 - $43:FFFF $31F $63:E000 - $63:FFFF
$120 $24:0000 - $24:1FFF $220 $44:0000 - $44:1FFF $320 $64:0000 - $64:1FFF
$121 $24:2000 - $24:3FFF $221 $44:2000 - $44:3FFF $321 $64:2000 - $64:3FFF
$122 $24:4000 - $24:5FFF $222 $44:4000 - $44:5FFF $322 $64:4000 - $64:5FFF
$123 $24:6000 - $24:7FFF $223 $44:6000 - $44:7FFF $323 $64:6000 - $64:7FFF
$124 $24:8000 - $24:9FFF $224 $44:8000 - $44:9FFF $324 $64:8000 - $64:9FFF
$125 $24:A000 - $24:BFFF $225 $44:A000 - $44:BFFF $325 $64:A000 - $64:BFFF
$126 $24:C000 - $24:DFFF $226 $44:C000 - $44:DFFF $326 $64:C000 - $64:DFFF
$127 $24:E000 - $24:FFFF $227 $44:E000 - $44:FFFF $327 $64:E000 - $64:FFFF
$128 $25:0000 - $25:1FFF $228 $45:0000 - $45:1FFF $328 $65:0000 - $65:1FFF
$129 $25:2000 - $25:3FFF $229 $45:2000 - $45:3FFF $329 $65:2000 - $65:3FFF
$12A $25:4000 - $25:5FFF $22A $45:4000 - $45:5FFF $32A $65:4000 - $65:5FFF
$12B $25:6000 - $25:7FFF $22B $45:6000 - $45:7FFF $32B $65:6000 - $65:7FFF
$12C $25:8000 - $25:9FFF $22C $45:8000 - $45:9FFF $32C $65:8000 - $65:9FFF
$12D $25:A000 - $25:BFFF $22D $45:A000 - $45:BFFF $32D $65:A000 - $65:BFFF
$12E $25:C000 - $25:DFFF $22E $45:C000 - $45:DFFF $32E $65:C000 - $65:DFFF
$12F $25:E000 - $25:FFFF $22F $45:E000 - $45:FFFF $32F $65:E000 - $65:FFFF
$130 $26:0000 - $26:1FFF $230 $46:0000 - $46:1FFF $330 $66:0000 - $66:1FFF
$131 $26:2000 - $26:3FFF $231 $46:2000 - $46:3FFF $331 $66:2000 - $66:3FFF
$132 $26:4000 - $26:5FFF $232 $46:4000 - $46:5FFF $332 $66:4000 - $66:5FFF
$133 $26:6000 - $26:7FFF $233 $46:6000 - $46:7FFF $333 $66:6000 - $66:7FFF
$134 $26:8000 - $26:9FFF $234 $46:8000 - $46:9FFF $334 $66:8000 - $66:9FFF
$135 $26:A000 - $26:BFFF $235 $46:A000 - $46:BFFF $335 $66:A000 - $66:BFFF
$136 $26:C000 - $26:DFFF $236 $46:C000 - $46:DFFF $336 $66:C000 - $66:DFFF
$137 $26:E000 - $26:FFFF $237 $46:E000 - $46:FFFF $337 $66:E000 - $66:FFFF
$138 $27:0000 - $27:1FFF $238 $47:0000 - $47:1FFF $338 $67:0000 - $67:1FFF
$139 $27:2000 - $27:3FFF $239 $47:2000 - $47:3FFF $339 $67:2000 - $67:3FFF
$13A $27:4000 - $27:5FFF $23A $47:4000 - $47:5FFF $33A $67:4000 - $67:5FFF
$13B $27:6000 - $27:7FFF $23B $47:6000 - $47:7FFF $33B $67:6000 - $67:7FFF
$13C $27:8000 - $27:9FFF $23C $47:8000 - $47:9FFF $33C $67:8000 - $67:9FFF
$13D $27:A000 - $27:BFFF $23D $47:A000 - $47:BFFF $33D $67:A000 - $67:BFFF
$13E $27:C000 - $27:DFFF $23E $47:C000 - $47:DFFF $33E $67:C000 - $67:DFFF
$13F $27:E000 - $27:FFFF $23F $47:E000 - $47:FFFF $33F $67:E000 - $67:FFFF
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