IO Pages: Difference between revisions

From F256 Foenix
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More detailed information is found in the [[Manuals]].
=== Notes ===
'''SRAM Address''': The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, Core2x has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 24-bit CPU-visible addresses.
'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.
== IO Page 0 ==
== IO Page 0 ==
{| class="wikitable"
{| class="wikitable"
Line 12: Line 19:
|
|
|
|
|Blue conversion
|Blue conversion table
|-
|-
|$C400 - $C4FF
|$C400 - $C4FF
Line 18: Line 25:
|
|
|
|
|Green conversion
|Green conversion table
|-
|-
|$C800 - $C8FF
|$C800 - $C8FF
Line 24: Line 31:
|
|
|
|
|Red conversion
|Red conversion table
|}
|}
=== Master Control Registers ($D0xx, $F0:10xx) ===
{| class="wikitable"
{| class="wikitable"
|+Master Control
|+Master Control
Line 212: Line 221:
|}
|}
{| class="wikitable"
{| class="wikitable"
|+Integer Math Coprocessor
|+Background Color
!MMU
!MMU
!Flat
!Flat
Line 226: Line 235:
!0
!0
|-
|-
|$DE00 - $DE01
|$D00D
|
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|
|
|RW
|RW
|MULU_A
|BGND_GREEN
| colspan="8" |Multiplication A (Unsigned 16-bit)
| colspan="8" |Background color Green component
|-
|-
|$DE00 - $DE02
|$D00F
|
|
|RW
|RW
|MULU_B
|BGND_RED
| colspan="8" |Multiplication B (Unsigned 16-bit)
| colspan="8" |Background color Red component
|}
{| class="wikitable"
|+Text Cursor
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$DE04 - $DE05
|$D010
|
|
|RW
|RW
|DIVU_DEN
|CCR
| colspan="8" |Denominator (Unsigned 16-bit)
|
|
|
|
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|-
|$DE06 - $DE07
|$D012
|
|
|RW
|RW
|DIVU_NUM
|CCH
| colspan="8" |Numerator (Unsigned 16-bit)
| colspan="8" |Cursor character code
|-
|-
|$DE08 - $DE0B
|$D014 - $D015
|
|
|RW
|RW
|ADD_A
|CURX
| colspan="8" |Addition A (Unsigned 32-bit)
| colspan="8" |Cursor X position (16-bit)
|-
|-
|$DE0C - $DE0F
|$D016 - $D017
|
|
|RW
|RW
|ADD_B
|CURY
| colspan="8" |Addition B (Unsigned 32-bit)
| colspan="8" |Cursor Y position (16-bit)
|}
{| class="wikitable"
|+Cursor Flash Rate
!Value
!Rate
|-
|0
|1 second
|-
|1
|1/2 second
|-
|2
|1/4 second
|-
|3
|1/8 second
|}
{| class="wikitable"
|+Raster
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$D018 - $D019
|
|
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A - $D01B
|
|
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|
|
|W
|LINT_CTRL
|
|
|
|
Line 272: Line 353:
|
|
|
|
|ENABLE
|-
|$D019 - $D01A
|
|
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}
=== Bitmap Control Registers ($D1xx, $F0:11xx) ===
{| class="wikitable"
|+Bitmaps
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|
|RW
|
|
|
|
|
|
| colspan="2" |CLUT
|ENABLE
|-
|$D101 - $D103
|
|RW
|
|
| colspan="8" |SRAM Address of bitmap 0 pixels (24-bit)
|-
|-
|$DE10 - $DE13
|$D108
|
|
|RW
|RW
|MULU
|
| colspan="8" |Multiplication A×B (Unsigned 32-bit)
|
|
|
|
|
| colspan="2" |CLUT
|ENABLE
|-
|-
|$DE14 - $DE15
|$D109 - $D10B
|
|
|RW
|RW
|QUOU
|
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
| colspan="8" |SRAM Address of bitmap 1 pixels (24-bit)
|-
|-
|$DE16 - $DE17
|$D110
|
|
|RW
|RW
|REMU
|
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|
|
|
|
|
| colspan="2" |CLUT
|ENABLE
|-
|-
|$DE18 - $DE1B
|$D111 - $D103
|
|
|RW
|RW
|ADD_R
|
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
| colspan="8" |SRAM Address of bitmap 2 pixels (24-bit)
|}
 
=== Tilemap Control Registers ($D2xx, $F0:12xx) ===
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|
|
|
| colspan="8" |Tilemap 2
|}
{| class="wikitable"
|+Tilemap
!Offset
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$00
|W
|
|
|
|
|TILE_SIZE_8
|
|
|
|ENABLE
|-
|$01 - $03
|W
|
| colspan="8" |SRAM Address of tile map entries (24-bit)
|-
|$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|$08
|W
|
| colspan="4" |X[3:0]
| colspan="4" |SSX
|-
|$09
|W
|
|—
|—
| colspan="6" |X[9:4]
|-
|$0A
|W
|
| colspan="4" |Y[3:0]
| colspan="4" |SSY
|-
|$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Y[7:4]
|}
{| class="wikitable"
|+Tilesets
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280 - $D283
|
|
|
| colspan="8" |Tileset 0
|-
|$D284 - $D287
|
|
|
| colspan="8" |Tileset 1
|-
|$D288 - $D28B
|
|
|
| colspan="8" |Tileset 2
|-
|$D28C - $D28F
|
|
|
| colspan="8" |Tileset 3
|-
|$D290 - $D293
|
|
|
| colspan="8" |Tileset 4
|-
|$D294 - $D298
|
|
|
| colspan="8" |Tileset 5
|-
|$D298 - $D29B
|
|
|
| colspan="8" |Tileset 6
|-
|$D29C - $D29F
|
|
|
| colspan="8" |Tileset 7
|}
{| class="wikitable"
|+Tileset
!Offset
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0 - 2
|W
|
| colspan="8" |SRAM Address of tile pixels (24-bit)
|-
|3
|W
|
|
|
|
|
|SQUARE
|
|
|
|}
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.
{| class="wikitable"
{| class="wikitable"
|+
|+
Line 315: Line 644:
!0
!0
|-
|-
|$D400
|
|
|
| colspan="8" |Left SID
|-
|$D500
|
|
|
| colspan="8" |Right SID
|}
{| class="wikitable"
|+SID Registers
!Offset
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +$00 - $01
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
| +$02 - $03
|W
|
| colspan="8" |Pulse width (12-bit)
|-
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
| +$05
|W
|
| colspan="4" |ATTACK
|DELAY
|
|
|
|-
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
| +$07 - $08
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
| +$09 - $0A
|W
|
| colspan="8" |Pulse width (12-bit)
|-
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
| +$0C
|W
|
| colspan="4" |ATTACK
|DELAY
|
|
|
|-
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
| +$0E - $0F
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
| +$10 - $11
|W
|
| colspan="8" |Pulse width (12-bit)
|-
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
| +$13
|W
|
| colspan="4" |ATTACK
|DELAY
|
|
|
|-
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}
{| class="wikitable"
|+OPL3 Registers (NOT ON F256JR)
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}
{| class="wikitable"
|+PSG Registers
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|
|
|
| colspan="8" |PSG Left
|-
|$D608
|
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|
|
|
| colspan="8" |PSG Right
|}
Note the stereo separation is controlled with the '''PSG_ST''' flag.
{| class="wikitable"
|+CODEC Registers
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}
{| class="wikitable"
|+UART Registers
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630 - $D631
|
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}
{| class="wikitable"
|+PS/2 Registers
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}
{| class="wikitable"
|+Timer Registers
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651 - $D653
|
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|
|
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655 - $D657
|
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659 - $D65B
|
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D - $D65F
|
|
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
{| class="wikitable"
|+RTC Registers
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|
|
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|
|
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|
|
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|
|
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|
|
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|
|
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|
|
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|
|
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|
|
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|
|
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|-
|$D69A
|
|
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|
|
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|
|
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|
|
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|
|
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|
|
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}
{| class="wikitable"
|+Text mode CLUT
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|
|
|W
|
|
| colspan="8" |Text foreground colors (16 × BGRx)
|-
|$D840 - $D87F
|
|
|W
|
|
| colspan="8" |Text background colors (16 × BGRx)
|}
{| class="wikitable"
|+Integer Math Coprocessor
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00 - $DE01
|
|
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE00 - $DE02
|
|
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|-
|$DE04 - $DE05
|
|
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06 - $DE07
|
|
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08 - $DE0B
|
|
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C - $DE0F
|
|
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
|
|
|
|
| colspan="8" |
|-
|$DE10 - $DE13
|
|
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14 - $DE15
|
|
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16 - $DE17
|
|
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18 - $DE1B
|
|
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.


== IO Page 1 ==
== IO Page 1 ==
Line 365: Line 1,503:
|-
|-
|$C000 - $C7FF
|$C000 - $C7FF
|$F0:4000 - $F0:47FF
|$F0:2000 - $F0:27FF
|
|
|
|
Line 371: Line 1,509:
|-
|-
|$C800 - $CFFF
|$C800 - $CFFF
|$F0:4800 - $F0:4FFF
|$F0:2800 - $F0:2FFF
|
|
|
|
Line 386: Line 1,524:
|-
|-
|$D000 - $D3FF
|$D000 - $D3FF
|$F0:5000 - $F0:53FF
|$F0:3000 - $F0:33FF
|
|
|
|
Line 392: Line 1,530:
|-
|-
|$D400 - $D7FF
|$D400 - $D7FF
|$F0:5400 - $F0:57FF
|$F0:3400 - $F0:37FF
|
|
|
|
Line 398: Line 1,536:
|-
|-
|$D800 - $DBFF
|$D800 - $DBFF
|$F0:5800 - $F0:5BFF
|$F0:3800 - $F0:3BFF
|
|
|
|
Line 404: Line 1,542:
|-
|-
|$DC00 - $DFFF
|$DC00 - $DFFF
|$F0:5C00 - $F0:5FFF
|$F0:3C00 - $F0:3FFF
|
|
|
|
Line 410: Line 1,548:
|}
|}
The 4th byte ('x') in each entry is unused.
The 4th byte ('x') in each entry is unused.
== IO Page 2 ==
{| class="wikitable"
|+
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.
80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
== IO Page 3 ==
{| class="wikitable"
|+
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

Revision as of 18:06, 8 October 2025

More detailed information is found in the Manuals.

Notes

SRAM Address: The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, Core2x has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 24-bit CPU-visible addresses.

Model names: Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

IO Page 0

Gamma Lookup
MMU Flat R/W Name Description
$C000 - $C0FF $F0:0000 - $F0:00FF Blue conversion table
$C400 - $C4FF $F0:0400 - $F0:04FF Green conversion table
$C800 - $C8FF $F0:0800 - $F0:08FF Red conversion table

Master Control Registers ($D0xx, $F0:10xx)

Master Control
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D000 $F0:1000 RW MSTR_CTRL_0 — GAMMA SPRITE TILE BITMAP GRAPH OVRLY TEXT
$D001 $F0:1001 RW MSTR_CTRL_1 — — FON_SET FON_OVLY MON_SLP DBL_Y DBL_X CLK_70

TEXT: Enable text layer

OVRLY: Overlay text on graphics, by making text background transparent. See FON_OVLY

GRAPH: Enable graphics layers (tile, sprites, bitmaps)

BITMAP: Enable bitmap layers (if GRAPH is also set)

TILE: Enable tile layers (if GRAPH is also set)

SPRITE: Enable sprite layers (if GRAPH is also set)

GAMMA: Enable gamma correction

CLK_70: Enable 400p70, else 480p60

DBL_X, DBL_Y: Double text mode character width & height

MON_SLP: Turn off monitor SYNC, putting it into sleep mode

FON_OVLY: Only BG color 0 is transparent in OVRLY mode. Else, all BG colors are transparent.

FON_SET: Chooses font set 0 or 1

Layer Configuration
MMU Flat R/W 7 6 5 4 3 2 1 0
$D002 RW — Layer 1 — Layer 0
$D003 RW — — — — — Layer 2

There are 6 configurable graphics maps that can be placed into any of the 3 visible layers. Layer 0 is the front graphics layer.

Layer Codes
Code Graphics Map
0 Bitmap 0
1 Bitmap 1
2 Bitmap 2
4 Tilemap 0
5 Tilemap 1
6 Tilemap 2
Border
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D004 RW BRDR_CTRL — SCROLL_X — — — ENABLE
$D005 RW BRDR_BLUE Border color Blue component
$D006 RW BRDR_GREEN Border color Green component
$D007 RW BRDR_RED Border color Red component
$D008 RW BRDR_WIDTH — — — SIZE_X
$D009 RW BRDR_HEIGHT — — — SIZE_Y
Background Color
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D00D RW BGND_BLUE Background color Blue component
$D00E RW BGND_GREEN Background color Green component
$D00F RW BGND_RED Background color Red component
Text Cursor
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D010 RW CCR FLASH_DIS RATE ENABLE
$D012 RW CCH Cursor character code
$D014 - $D015 RW CURX Cursor X position (16-bit)
$D016 - $D017 RW CURY Cursor Y position (16-bit)
Cursor Flash Rate
Value Rate
0 1 second
1 1/2 second
2 1/4 second
3 1/8 second
Raster
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D018 - $D019 R RAST_COL Raster current column (12-bit)
$D01A - $D01B R RAST_ROW Raster current row (12-bit)
$D018 W LINT_CTRL ENABLE
$D019 - $D01A W LINT_L Line interrupt line (12-bit)

Bitmap Control Registers ($D1xx, $F0:11xx)

Bitmaps
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D100 RW CLUT ENABLE
$D101 - $D103 RW SRAM Address of bitmap 0 pixels (24-bit)
$D108 RW CLUT ENABLE
$D109 - $D10B RW SRAM Address of bitmap 1 pixels (24-bit)
$D110 RW CLUT ENABLE
$D111 - $D103 RW SRAM Address of bitmap 2 pixels (24-bit)

Tilemap Control Registers ($D2xx, $F0:12xx)

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D200 Tilemap 0
$D20C Tilemap 1
$D218 Tilemap 2
Tilemap
Offset R/W Name 7 6 5 4 3 2 1 0
$00 W TILE_SIZE_8 ENABLE
$01 - $03 W SRAM Address of tile map entries (24-bit)
$04 W MAP_SIZE_X (8-bit)
$06 W MAP_SIZE_Y (8-bit)
$08 W X[3:0] SSX
$09 W — — X[9:4]
$0A W Y[3:0] SSY
$0B W — — — — Y[7:4]
Tilesets
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D280 - $D283 Tileset 0
$D284 - $D287 Tileset 1
$D288 - $D28B Tileset 2
$D28C - $D28F Tileset 3
$D290 - $D293 Tileset 4
$D294 - $D298 Tileset 5
$D298 - $D29B Tileset 6
$D29C - $D29F Tileset 7
Tileset
Offset R/W Name 7 6 5 4 3 2 1 0
0 - 2 W SRAM Address of tile pixels (24-bit)
3 W SQUARE
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D400 Left SID
$D500 Right SID
SID Registers
Offset R/W Name 7 6 5 4 3 2 1 0
+$00 - $01 W Voice 1 Frequency (16-bit)
+$02 - $03 W Pulse width (12-bit)
+$04 W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$05 W ATTACK DELAY
+$06 W SUSTAIN RELEASE
+$07 - $08 W Voice 2 Frequency (16-bit)
+$09 - $0A W Pulse width (12-bit)
+$0B W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$0C W ATTACK DELAY
+$0D W SUSTAIN RELEASE
+$0E - $0F W Voice 3 Frequency (16-bit)
+$10 - $11 W Pulse width (12-bit)
+$12 W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$13 W ATTACK DELAY
+$14 W SUSTAIN RELEASE
+$15 W Misc — — — — — FC[2:0]
+$16 W FC[10:3]
+$17 W RESONANCE EXT FILTV3 FILTV2 FILTV1
+$18 W MUTEV3 HIGH BAND LOW VOLUME
OPL3 Registers (NOT ON F256JR)
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D580 W Address registers for ports $000 - $0FF
$D581 W Data registers for all ports
$D582 W Address register for ports $100 - $1FF
PSG Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D600 PSG Left
$D608 PSG Left + Right
$D610 PSG Right

Note the stereo separation is controlled with the PSG_ST flag.

CODEC Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D620 W DATA[7:0]
$D621 W REGISTER DATA[8]
$D622 R — — — — — — — BUSY
W — — — — — — — START
UART Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
DLAB = 0
$D630 R RXD RX_DATA
W TXR TX_DATA
$D631 RW IER — — — — STAT ERR TXE RXA
DLAB = 1
$D630 - $D631 RW DL DIV (16-bit)
$D632 R IIR FIFO FIFO64 — STATE /PENDING
W FCR RXT FIFO64 — DMA TXR RXR FIFOE
$D633 RW LCR DLAB — PARITY STOP DATA
PS/2 Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D640 RW PS2_CTRL — — MCLR KCLR M_WR — K_WR —
$D641 RW PS2_OUT Data to keyboard
$D642 R KBD_IN Data in from keyboard FIFO
$D643 R MS_IN Data in from mouse FIFO
$D644 R PS2_STAT K_AK K_NK M_AK M_NK — — MEMP KEMP
Timer Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D650 W T0_CTR — — — — UP LD CLR EN
R T0_STAT — — — — — — — EQ
$D651 - $D653 RW T0_VAL VAL (24-bit)
$D654 RW T0_CMP_CTR — — — — — — RELD RECLR
$D655 - $D657 RW T0_CMP CMP (24-bit)
$D658 W T1_CTR — — — — UP LD CLR EN
R T1_STAT — — — — — — — EQ
$D659 - $D65B RW T1_VAL VAL (24-bit)
$D65C RW T1_CMP_CTR — — — — — — RELD RECLR
$D65D - $D65F RW T1_CMP CMP (24-bit)
RTC Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D690 RW Seconds 0 10s digit 1s digit
$D691 RW Seconds Alarm 0 10s digit 1s digit
$D692 RW Minutes 0 10s digit 1s digit
$D693 RW Minutes Alarm 0 10s digit 1s digit
$D694 RW Hours AM/PM 0 10s digit 1s digit
$D695 RW Hours Alarm AM/PM 0 10s digit 1s digit
$D696 RW Days 0 0 10s digit 1s digit
$D697 RW Days Alarm 0 0 10s digit 1s digit
$D698 RW Day of Week 0 0 0 0 0 1s digit
$D699 RW Month 0 0 0 10s digit 1s digit
$D69A RW Year 10s digit 1s digit
$D69B RW Rates 0 WD RS
$D69C RW Enables 0 0 0 0 AIE PIE PWRIE ABE
$D69D RW Flags 0 0 0 0 AF PF PWRF BVF
$D69E RW Control 0 0 0 0 UTI STOP 12/24 DSE
$D69F RW Century 10s digit 1s digit
Text mode CLUT
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D800 - $D83F W Text foreground colors (16 × BGRx)
$D840 - $D87F W Text background colors (16 × BGRx)
Integer Math Coprocessor
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DE00 - $DE01 RW MULU_A Multiplication A (Unsigned 16-bit)
$DE00 - $DE02 RW MULU_B Multiplication B (Unsigned 16-bit)
$DE04 - $DE05 RW DIVU_DEN Division Denominator (Unsigned 16-bit)
$DE06 - $DE07 RW DIVU_NUM Division Numerator (Unsigned 16-bit)
$DE08 - $DE0B RW ADD_A Addition A (Unsigned 32-bit)
$DE0C - $DE0F RW ADD_B Addition B (Unsigned 32-bit)
$DE10 - $DE13 RW MULU Multiplication A×B Result (Unsigned 32-bit)
$DE14 - $DE15 RW QUOU Quotient of Num/Den (Unsigned 16-bit)
$DE16 - $DE17 RW REMU Remainder of Num/Den (Unsigned 16-bit)
$DE18 - $DE1B RW ADD_R Addition A+B Result (Unsigned 32-bit)

Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

IO Page 1

Text Mode Font Sets
MMU Flat R/W Name Description
$C000 - $C7FF $F0:2000 - $F0:27FF Font set 0 (256 × 8-byte chars)
$C800 - $CFFF $F0:2800 - $F0:2FFF Font set 1 (256 × 8-byte chars)

Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

Graphics CLUTS
MMU Flat R/W Name Description
$D000 - $D3FF $F0:3000 - $F0:33FF Graphics CLUT 0 (256 × BGRx)
$D400 - $D7FF $F0:3400 - $F0:37FF Graphics CLUT 1 (256 × BGRx)
$D800 - $DBFF $F0:3800 - $F0:3BFF Graphics CLUT 2 (256 × BGRx)
$DC00 - $DFFF $F0:3C00 - $F0:3FFF Graphics CLUT 3 (256 × BGRx)

The 4th byte ('x') in each entry is unused.

IO Page 2

MMU Flat R/W Name Description
$C000 - $DFFF $F0:4000 - $F0:5FFF RW Text screen character matrix

1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.

IO Page 3

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$C000 - $DFFF $F0:6000 - $F0:7FFF RW Text screen color matrix
FG color (0-15) BG color (0-15)

Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

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