IO Pages: Difference between revisions

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'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.
'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.


<span id="BGRx>'''BGRx'''</span>: A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.
<span id="BGR">'''BGR'''</span>: A 3-byte color entry in Blue, Green, Red order.
 
<span id="BGRx">'''BGRx'''</span>: A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.


== IO Page 0 ==
== IO Page 0 ==
Line 1,212: Line 1,214:
|-
|-
|$D660
|$D660
|
|$F0:1660
|
|
|INT_PENDING
|INT_PENDING
Line 1,218: Line 1,220:
|-
|-
|$D664
|$D664
|
|$F0:1664
|
|
|INT_POLARITY
|INT_POLARITY
Line 1,224: Line 1,226:
|-
|-
|$D668
|$D668
|
|$F0:1668
|
|
|INT_EDGE
|INT_EDGE
Line 1,230: Line 1,232:
|-
|-
|$D66C
|$D66C
|
|$F0:166C
|
|
|INT_MASK
|INT_MASK
Line 1,236: Line 1,238:
|-
|-
|
|
| +0 & $01
|
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
|
| +0 & $02
|
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
|
| +0 & $04
|
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
|
| +0 & $08
|
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
|
| +0 & $10
|
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
|
| +0 & $20
|
|
|}
|INT_TIMER_1
{| class="wikitable"
| colspan="8" |TIMER1 has reached its target value
|+Interrupt flags
!Offset
!Mask
!Name
!Description
|-
|-
|0
|
|$01
| +0 & $80
|INT_VKY_SOF
|
|Start of Frame interrupt (beginning of VSYNC)
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|-
|0
|
|$02
|
|INT_VKY_SOL
|
|Start of Line interrupt
|
|-
| colspan="8" |
|0
|$04
|INT_PS2_KBD
|PS/2 keyboard event
|-
|0
|$08
|INT_PS2_MOUSE
|PS/2 mouse event
|-
|0
|$10
|INT_TIMER_0
|TIMER0 has reached its target value
|-
|0
|$20
|INT_TIMER_1
|TIMER1 has reached its target value
|-
|0
|$80
|INT_CARTRIDGE
|Interrupt asserted from cartridge port
|-
|-
|
|
| +1 & $01
|
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
|
| +1 & $10
|
|
|-
|1
|$01
|INT_UART
|The UART is ready to receive or send data
|-
|1
|$10
|INT_RTC
|INT_RTC
|Interrupt from real time clock chip
| colspan="8" |Interrupt from real time clock chip
|-
|-
|1
|
|$20
| +1 & $20
|
|INT_VIA0
|INT_VIA0
|Event from the joystick VIA chip
| colspan="8" |Event from the joystick VIA chip
|-
|-
|1
|
|$40
| +1 & $40
|
|INT_VIA1
|INT_VIA1
|Event from the keyboard VIA chip (F256k Series Only!)
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|-
|1
|
|$80
| +1 & $80
|
|INT_SDC_INS
|INT_SDC_INS
|SD Card has been inserted
| colspan="8" |SD Card has been inserted
|-
|-
|
|
Line 1,324: Line 1,319:
|
|
|
|
| colspan="8" |
|-
|-
|2
|
|$01
| +2 & $01
|
|IEC_DATA_i
|IEC_DATA_i
|IEC data in
| colspan="8" |IEC data in
|-
|-
|2
|
|$02
| +2 & $02
|
|IEC_CLK_i
|IEC_CLK_i
|IEC clock in
| colspan="8" |IEC clock in
|-
|-
|2
|
|$04
| +2 & $04
|
|IEC_ATN_i
|IEC_ATN_i
|IEC attention in
| colspan="8" |IEC attention in
|-
|-
|2
|
|$08
| +2 & $08
|
|IEC_SREQ_i
|IEC_SREQ_i
|IEC service request in
| colspan="8" |IEC service request in
|}
|}
{| class="wikitable"
{| class="wikitable"
Line 1,361: Line 1,361:
|-
|-
|$D670
|$D670
|
|$F0:1670
|R
|R
|
|
Line 1,386: Line 1,386:
|-
|-
|$D680
|$D680
|
|$F0:1680
|R
|R
|IEC_I
|IEC_I
Line 1,399: Line 1,399:
|-
|-
|$D681
|$D681
|
|$F0:1681
|RW
|RW
|IEC_O
|IEC_O
Line 1,427: Line 1,427:
|-
|-
|$D690
|$D690
|
|$F0:1690
|RW
|RW
|Seconds
|Seconds
Line 1,435: Line 1,435:
|-
|-
|$D691
|$D691
|
|$F0:1691
|RW
|RW
|Seconds Alarm
|Seconds Alarm
Line 1,443: Line 1,443:
|-
|-
|$D692
|$D692
|
|$F0:1692
|RW
|RW
|Minutes
|Minutes
Line 1,451: Line 1,451:
|-
|-
|$D693
|$D693
|
|$F0:1693
|RW
|RW
|Minutes Alarm
|Minutes Alarm
Line 1,459: Line 1,459:
|-
|-
|$D694
|$D694
|
|$F0:1694
|RW
|RW
|Hours
|Hours
Line 1,468: Line 1,468:
|-
|-
|$D695
|$D695
|
|$F0:1695
|RW
|RW
|Hours Alarm
|Hours Alarm
Line 1,477: Line 1,477:
|-
|-
|$D696
|$D696
|
|$F0:1696
|RW
|RW
|Days
|Days
Line 1,486: Line 1,486:
|-
|-
|$D697
|$D697
|
|$F0:1697
|RW
|RW
|Days Alarm
|Days Alarm
Line 1,495: Line 1,495:
|-
|-
|$D698
|$D698
|
|$F0:1698
|RW
|RW
|Day of Week
|Day of Week
Line 1,506: Line 1,506:
|-
|-
|$D699
|$D699
|
|$F0:1699
|RW
|RW
|Month
|Month
Line 1,516: Line 1,516:
|-
|-
|$D69A
|$D69A
|
|$F0:169A
|RW
|RW
|Year
|Year
Line 1,523: Line 1,523:
|-
|-
|$D69B
|$D69B
|
|$F0:169B
|RW
|RW
|Rates
|Rates
Line 1,531: Line 1,531:
|-
|-
|$D69C
|$D69C
|
|$F0:169C
|RW
|RW
|Enables
|Enables
Line 1,544: Line 1,544:
|-
|-
|$D69D
|$D69D
|
|$F0:169D
|RW
|RW
|Flags
|Flags
Line 1,557: Line 1,557:
|-
|-
|$D69E
|$D69E
|
|$F0:169E
|RW
|RW
|Control
|Control
Line 1,570: Line 1,570:
|-
|-
|$D69F
|$D69F
|
|$F0:169F
|RW
|RW
|Century
|Century
Line 1,592: Line 1,592:
|-
|-
|$D6A0
|$D6A0
|
|$F0:16A0
|W
|W
|SYS0
|SYS0
Line 1,618: Line 1,618:
|-
|-
|$D6A1
|$D6A1
|
|$F0:16A1
|RW
|RW
|SYS1
|SYS1
Line 1,643: Line 1,643:
!0
!0
|-
|-
|$D6A7 - $D6A9
|$D6A7
|
|$F0:16A7
|W
|W
|
|
| colspan="8" |Power LED color (BGR)
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|-
|$D6AA - $D6AC
|$D6AA
|
|$F0:16AA
|W
|W
|
|
| colspan="8" |Media LED color (BGR)
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|-
|$D6AD - $D6AF
|$D6AD
|
|$F0:16AD
|W
|W
|
|
| colspan="8" |Shift LED color (BGR)
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|}
|}
{| class="wikitable"
{| class="wikitable"
Line 1,677: Line 1,677:
|-
|-
|$D6A7
|$D6A7
|
|$F0:16A7
|R
|R
|MID
|MID
Line 1,686: Line 1,686:
|-
|-
|$D6A8
|$D6A8
|
|$F0:16A8
|R
|R
|PCBID0
|PCBID0
Line 1,692: Line 1,692:
|-
|-
|$D6A9
|$D6A9
|
|$F0:16A9
|R
|R
|PCBID1
|PCBID1
Line 1,698: Line 1,698:
|-
|-
|$D6AA
|$D6AA
|
|$F0:16AA
|R
|R
|CHSV
|CHSV
Line 1,704: Line 1,704:
|-
|-
|$D6AC
|$D6AC
|
|$F0:16AC
|R
|R
|CHV
|CHV
Line 1,710: Line 1,710:
|-
|-
|$D6AE
|$D6AE
|
|$F0:16AE
|R
|R
|CHN
|CHN
Line 1,731: Line 1,731:
|-
|-
|$D6E0
|$D6E0
|
|$F0:16E0
|W
|W
|
|
Line 1,744: Line 1,744:
|-
|-
|$D6E2
|$D6E2
|
|$F0:16E2
|RW
|RW
|
|
Line 1,750: Line 1,750:
|-
|-
|$D6E4
|$D6E4
|
|$F0:16E4
|RW
|RW
|
|
Line 1,756: Line 1,756:
|-
|-
|$D6E6
|$D6E6
|
|$F0:16E6
|W
|W
|
|
Line 1,762: Line 1,762:
|-
|-
|$D6E7
|$D6E7
|
|$F0:16E7
|W
|W
|
|
Line 1,768: Line 1,768:
|-
|-
|$D6E8
|$D6E8
|
|$F0:16E8
|W
|W
|
|
Line 1,789: Line 1,789:
|-
|-
|$D6EB
|$D6EB
|
|$F0:16EB
|R
|R
|PCBMA
|PCBMA
Line 1,795: Line 1,795:
|-
|-
|$D6EC
|$D6EC
|
|$F0:16EC
|R
|R
|PCBMI
|PCBMI
Line 1,801: Line 1,801:
|-
|-
|$D6ED
|$D6ED
|
|$F0:16ED
|R
|R
|PCBD
|PCBD
Line 1,807: Line 1,807:
|-
|-
|$D6EE
|$D6EE
|
|$F0:16EE
|R
|R
|PCBM
|PCBM
Line 1,813: Line 1,813:
|-
|-
|$D6EF
|$D6EF
|
|$F0:16EF
|R
|R
|PCBY
|PCBY
Line 1,834: Line 1,834:
|-
|-
|$D800 - $D83F
|$D800 - $D83F
|
|$F0:1800 - $F0:183F
|W
|W
|
|
Line 1,840: Line 1,840:
|-
|-
|$D840 - $D87F
|$D840 - $D87F
|
|$F0:1840 - $F0:187f
|W
|W
|
|
Line 1,861: Line 1,861:
|-
|-
|$D900 - $DAFF
|$D900 - $DAFF
|
|$F0:1900 - $F0:1AFF
|
|
|
|
Line 1,916: Line 1,916:
|-
|-
|$DB00
|$DB00
|
|$F0:1B00
|
|
|VIA1
|VIA1
Line 1,922: Line 1,922:
|-
|-
|$DC00
|$DC00
|
|$F0:1C00
|
|
|VIA0
|VIA0
Line 2,042: Line 2,042:
|-
|-
|$DD00
|$DD00
|
|$F0:1D00
|RW
|RW
|
|
Line 2,055: Line 2,055:
|-
|-
|$DD01
|$DD01
|
|$F0:1D01
|RW
|RW
|
|
Line 2,076: Line 2,076:
!0
!0
|-
|-
|$DE00 - $DE01
|$DE00
|
|$F0:1E00
|RW
|RW
|MULU_A
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|-
|$DE00 - $DE02
|$DE02
|
|$F0:1E02
|RW
|RW
|MULU_B
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|-
|$DE04 - $DE05
|$DE04
|
|$F0:1E04
|RW
|RW
|DIVU_DEN
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|-
|$DE06 - $DE07
|$DE06
|
|$F0:1E06
|RW
|RW
|DIVU_NUM
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|-
|$DE08 - $DE0B
|$DE08
|
|$F0:1E08
|RW
|RW
|ADD_A
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|-
|$DE0C - $DE0F
|$DE0C
|
|$F0:1E0C
|RW
|RW
|ADD_B
|ADD_B
Line 2,118: Line 2,118:
| colspan="8" |
| colspan="8" |
|-
|-
|$DE10 - $DE13
|$DE10
|
|$F0:1E10
|RW
|RW
|MULU
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|-
|$DE14 - $DE15
|$DE14
|
|$F0:1E14
|RW
|RW
|QUOU
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|-
|$DE16 - $DE17
|$DE16
|
|$F0:1E16
|RW
|RW
|REMU
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|-
|$DE18 - $DE1B
|$DE18
|
|$F0:1E18
|RW
|RW
|ADD_R
|ADD_R
Line 2,159: Line 2,159:
|-
|-
|$DF00
|$DF00
|
|$F0:1F00
|RW
|RW
|
|
Line 2,172: Line 2,172:
|-
|-
|$DF01
|$DF01
|
|$F0:1F01
|W
|W
|
|
Line 2,178: Line 2,178:
|-
|-
|$DF04
|$DF04
|
|$F0:1F04
|RW
|RW
|
|
Line 2,184: Line 2,184:
|-
|-
|$DF08
|$DF08
|
|$F0:1F08
|RW
|RW
|
|
Line 2,190: Line 2,190:
|-
|-
|$DF0C
|$DF0C
|
|$F0:1F0C
|RW
|RW
|
|
| colspan="8" |Count (24-bit, not 2D mode)
| colspan="8" |Count (24-bit, not 2D mode)
|-
|-
|$DF0C
|
|
|
|RW
|RW
Line 2,202: Line 2,202:
|-
|-
|$DF0E
|$DF0E
|
|$F0:1F0E
|RW
|RW
|
|
Line 2,208: Line 2,208:
|-
|-
|$DF10
|$DF10
|
|$F0:1F10
|RW
|RW
|
|
Line 2,214: Line 2,214:
|-
|-
|$DF12
|$DF12
|
|$F0:1F12
|RW
|RW
|
|

Revision as of 12:27, 9 October 2025

More detailed information is found in the Manuals.

Notes

SRAM Address: Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, Core2x has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 24-bit CPU-visible addresses.

Model names: Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

BGR: A 3-byte color entry in Blue, Green, Red order.

BGRx: A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

IO Page 0

Gamma Lookup
MMU Flat R/W Name Description
$C000 - $C0FF $F0:0000 - $F0:00FF Blue gamma conversion table
$C400 - $C4FF $F0:0400 - $F0:04FF Green gamma conversion table
$C800 - $C8FF $F0:0800 - $F0:08FF Red gamma conversion table
Mouse Pointer
MMU Flat R/W Name Description
$CC00 - $CCFF $F0:0C00 - $F0:0CFF Mouse pointer bitmap (16×16 greyscale bytes)

Master Control Registers ($D0xx, $F0:10xx)

Master Control
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D000 $F0:1000 RW MSTR_CTRL_0 — GAMMA SPRITE TILE BITMAP GRAPH OVRLY TEXT
$D001 $F0:1001 RW MSTR_CTRL_1 — — FON_SET FON_OVLY MON_SLP DBL_Y DBL_X CLK_70

TEXT: Enable text layer

OVRLY: Overlay text on graphics, by making text background transparent. See FON_OVLY

GRAPH: Enable graphics layers (tile, sprites, bitmaps)

BITMAP: Enable bitmap layers (if GRAPH is also set)

TILE: Enable tile layers (if GRAPH is also set)

SPRITE: Enable sprite layers (if GRAPH is also set)

GAMMA: Enable gamma correction

CLK_70: Enable 400p70, else 480p60

DBL_X, DBL_Y: Double text mode character width & height

MON_SLP: Turn off monitor SYNC, putting it into sleep mode

FON_OVLY: Only BG color 0 is transparent in OVRLY mode. Else, all BG colors are transparent.

FON_SET: Chooses font set 0 or 1

Layer Configuration
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D002 $F0:1002 RW — Layer 1 — Layer 0
$D003 $F0:1003 RW — — — — — Layer 2
Values 0-2: Bitmap 0-2

4-6: Tilemap 0-2

Border
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D004 $F0:1004 RW BRDR_CTRL — SCROLL_X — — — ENABLE
$D005 $F0:1005 RW BRDR_BLUE Border color Blue component
$D006 $F0:1006 RW BRDR_GREEN Border color Green component
$D007 $F0:1007 RW BRDR_RED Border color Red component
$D008 $F0:1008 RW BRDR_WIDTH — — — SIZE_X
$D009 $F0:1009 RW BRDR_HEIGHT — — — SIZE_Y
Background Color
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D00D $F0:100D RW BGND_BLUE Background color Blue component
$D00E $F0:100E RW BGND_GREEN Background color Green component
$D00F $F0:100F RW BGND_RED Background color Red component
Text Cursor
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D010 $F0:1010 RW CCR FLASH_DIS RATE ENABLE
RATE 0: 1 second

1: 1/2 second 2: 1/4 second 3: 1/8 second

$D012 $F0:1012 RW CCH Cursor character code
$D014 $F0:1014 RW CURX Cursor X position (16-bit)
$D016 $F0:1016 RW CURY Cursor Y position (16-bit)
Raster
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D018 $F0:1018 R RAST_COL Raster current column (12-bit)
$D01A $F0:101A R RAST_ROW Raster current row (12-bit)
$D018 $F0:1018 W LINT_CTRL ENABLE
$D019 $F0:1019 W LINT_L Line interrupt line (12-bit)

Bitmap Control Registers ($D1xx, $F0:11xx)

Bitmaps
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D100 $F0:1100 RW CLUT ENABLE
$D101 $F0:1101 RW SRAM Address of bitmap 0 pixels (24-bit)
$D108 $F0:1108 RW CLUT ENABLE
$D109 $F0:1109 RW SRAM Address of bitmap 1 pixels (24-bit)
$D110 $F0:1110 RW CLUT ENABLE
$D111 $F0:1111 RW SRAM Address of bitmap 2 pixels (24-bit)

Tilemap Control Registers ($D2xx, $F0:12xx)

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D200 $F0:1200 Tilemap 0
$D20C $F0:120C Tilemap 1
$D218 $F0:1218 Tilemap 2
+$00 W TILE_SIZE_8 ENABLE
+$01 W SRAM Address of tile map entries (24-bit)
+$04 W MAP_SIZE_X (8-bit)
+$06 W MAP_SIZE_Y (8-bit)
+$08 W X[3:0] SSX
+$09 W — — X[9:4]
+$0A W Y[3:0] SSY
+$0B W — — — — Y[7:4]
Tilesets
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D280 $F0:1280 Tileset 0
$D284 $F0:1284 Tileset 1
$D288 $F0:1288 Tileset 2
$D28C $F0:128C Tileset 3
$D290 $F0:1290 Tileset 4
$D294 $F0:1294 Tileset 5
$D298 $F0:1298 Tileset 6
$D29C $F0:129C Tileset 7
+0 W SRAM Address of tile pixels (24-bit)
+3 W — — — — SQUARE — — —
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D400 $F0:1400 Left SID
$D500 $F0:1500 Right SID
+$00 W Voice 1 Frequency (16-bit)
+$02 W Pulse width (12-bit)
+$04 W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$05 W ATTACK DELAY
+$06 W SUSTAIN RELEASE
+$07 W Voice 2 Frequency (16-bit)
+$09 W Pulse width (12-bit)
+$0B W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$0C W ATTACK DELAY
+$0D W SUSTAIN RELEASE
+$0E W Voice 3 Frequency (16-bit)
+$10 W Pulse width (12-bit)
+$12 W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$13 W ATTACK DELAY
+$14 W SUSTAIN RELEASE
+$15 W Misc — — — — — FC[2:0]
+$16 W FC[10:3]
+$17 W RESONANCE EXT FILTV3 FILTV2 FILTV1
+$18 W MUTEV3 HIGH BAND LOW VOLUME
OPL3 Registers (NOT ON F256JR)
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D580 $F0:1580 W Address registers for ports $000 - $0FF
$D581 $F0:1581 W Data registers for all ports
$D582 $F0:1582 W Address register for ports $100 - $1FF
PSG Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D600 $F0:1600 PSG Left
$D608 $F0:1608 PSG Left + Right
$D610 $F0:1610 PSG Right

Note the stereo separation is controlled with the PSG_ST flag.

CODEC Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D620 $F0:1620 W DATA[7:0]
$D621 $F0:1621 W REGISTER DATA[8]
$D622 $F0:1622 R — — — — — — — BUSY
W — — — — — — — START
UART Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
DLAB = 0
$D630 $F0:1630 R RXD RX_DATA
W TXR TX_DATA
$D631 $F0:1631 RW IER — — — — STAT ERR TXE RXA
DLAB = 1
$D630 $F0:1630 RW DL DIV (16-bit)
$D632 $F0:1632 R IIR FIFO FIFO64 — STATE /PENDING
W FCR RXT FIFO64 — DMA TXR RXR FIFOE
$D633 $F0:1633 RW LCR DLAB — PARITY STOP DATA
PS/2 Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D640 $F0:1640 RW PS2_CTRL — — MCLR KCLR M_WR — K_WR —
$D641 $F0:1641 RW PS2_OUT Data to keyboard
$D642 $F0:1642 R KBD_IN Data in from keyboard FIFO
$D643 $F0:1643 R MS_IN Data in from mouse FIFO
$D644 $F0:1644 R PS2_STAT K_AK K_NK M_AK M_NK — — MEMP KEMP
Timer Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D650 $F0:1650 W T0_CTR — — — — UP LD CLR EN
R T0_STAT — — — — — — — EQ
$D651 $F0:1651 RW T0_VAL VAL (24-bit)
$D654 $F0:1654 RW T0_CMP_CTR — — — — — — RELD RECLR
$D655 $F0:1655 RW T0_CMP CMP (24-bit)
$D658 $F0:1658 W T1_CTR — — — — UP LD CLR EN
R T1_STAT — — — — — — — EQ
$D659 $F0:1659 RW T1_VAL VAL (24-bit)
$D65C $F0:165C RW T1_CMP_CTR — — — — — — RELD RECLR
$D65D $F0:165D RW T1_CMP CMP (24-bit)
Interrupt Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D660 $F0:1660 INT_PENDING Per-interrupt flags (24-bit)
$D664 $F0:1664 INT_POLARITY Per-interrupt flags (24-bit)
$D668 $F0:1668 INT_EDGE Per-interrupt flags (24-bit)
$D66C $F0:166C INT_MASK Per-interrupt flags (24-bit)
+0 & $01 INT_VKY_SOF Start of Frame interrupt (beginning of VSYNC)
+0 & $02 INT_VKY_SOL Start of Line interrupt
+0 & $04 INT_PS2_KBD PS/2 keyboard event
+0 & $08 INT_PS2_MOUSE PS/2 mouse event
+0 & $10 INT_TIMER_0 TIMER0 has reached its target value
+0 & $20 INT_TIMER_1 TIMER1 has reached its target value
+0 & $80 INT_CARTRIDGE Interrupt asserted from cartridge port
+1 & $01 INT_UART The UART is ready to receive or send data
+1 & $10 INT_RTC Interrupt from real time clock chip
+1 & $20 INT_VIA0 Event from the joystick VIA chip
+1 & $40 INT_VIA1 Event from the keyboard VIA chip (F256k Series Only!)
+1 & $80 INT_SDC_INS SD Card has been inserted
+2 & $01 IEC_DATA_i IEC data in
+2 & $02 IEC_CLK_i IEC clock in
+2 & $04 IEC_ATN_i IEC attention in
+2 & $08 IEC_SREQ_i IEC service request in
DIP Switches
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D670 $F0:1670 R GAMMA USER2 USER1 USER0 BOOT
IEC Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D680 $F0:1680 R IEC_I SRQ_i — — ATN_i — — CLK_i DAT_i
$D681 $F0:1681 RW IEC_O SRQ_o RST_o NMI_EN ATN_o — — CLK_o DAT_o
RTC Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D690 $F0:1690 RW Seconds 0 10s digit 1s digit
$D691 $F0:1691 RW Seconds Alarm 0 10s digit 1s digit
$D692 $F0:1692 RW Minutes 0 10s digit 1s digit
$D693 $F0:1693 RW Minutes Alarm 0 10s digit 1s digit
$D694 $F0:1694 RW Hours AM/PM 0 10s digit 1s digit
$D695 $F0:1695 RW Hours Alarm AM/PM 0 10s digit 1s digit
$D696 $F0:1696 RW Days 0 0 10s digit 1s digit
$D697 $F0:1697 RW Days Alarm 0 0 10s digit 1s digit
$D698 $F0:1698 RW Day of Week 0 0 0 0 0 1s digit
$D699 $F0:1699 RW Month 0 0 0 10s digit 1s digit
$D69A $F0:169A RW Year 10s digit 1s digit
$D69B $F0:169B RW Rates 0 WD RS
$D69C $F0:169C RW Enables 0 0 0 0 AIE PIE PWRIE ABE
$D69D $F0:169D RW Flags 0 0 0 0 AF PF PWRF BVF
$D69E $F0:169E RW Control 0 0 0 0 UTI STOP 12/24 DSE
$D69F $F0:169F RW Century 10s digit 1s digit
System Control Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6A0 $F0:16A0 W SYS0 RESET — CAP_EN BUZZ L1 L0 SD_L PWR_L
R — SD_WP SD_CD BUZZ L1 L0 SD_L PWR_L
$D6A1 $F0:16A1 RW SYS1 L1_RATE L0_RATE SID_ST PSG_ST L1_MN L0_MN
F256k Series LEDs
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6A7 $F0:16A7 W Power LED color (BGR)
$D6AA $F0:16AA W Media LED color (BGR)
$D6AD $F0:16AD W Shift LED color (BGR)
Machine ID and FPGA Core Versions
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6A7 $F0:16A7 R MID — — — ID
$D6A8 $F0:16A8 R PCBID0 ASCII character 0: "B" (See also $D6EB)
$D6A9 $F0:16A9 R PCBID1 ASCII character 1: "0"
$D6AA $F0:16AA R CHSV VICKY sub-version in BCD (16-bit)
$D6AC $F0:16AC R CHV VICKY version in BCD (16-bit)
$D6AE $F0:16AE R CHN VICKY number in BCD (16-bit)
Mouse Pointer Control
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6E0 $F0:16E0 W — — — — — — MODE EN
$D6E2 $F0:16E2 RW X (16-bit)
$D6E4 $F0:16E4 RW Y (16-bit)
$D6E6 $F0:16E6 W PS2_BYTE_0
$D6E7 $F0:16E7 W PS2_BYTE_1
$D6E8 $F0:16E8 W PS2_BYTE_2
PCB Information
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6EB $F0:16EB R PCBMA PCB Major Rev (ASCII)
$D6EC $F0:16EC R PCBMI PCB Minor Rev (ASCII)
$D6ED $F0:16ED R PCBD PCB Day (BCD)
$D6EE $F0:16EE R PCBM PCB Month (BCD)
$D6EF $F0:16EF R PCBY PCB Year (BCD)
Text mode CLUT
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D800 - $D83F $F0:1800 - $F0:183F W Text foreground colors (16 × BGRx)
$D840 - $D87F $F0:1840 - $F0:187f W Text background colors (16 × BGRx)
Sprite Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D900 - $DAFF $F0:1900 - $F0:1AFF 64 × 8-byte Sprite Registers
+0 W — SIZE LAYER LUT ENABLE
SIZE 0: 32×32, 1: 24×24, 2: 16×16, 3: 8×8
+1 W SRAM Address of sprite pixels (24-bit)
+4 W X position (16-bit)
+6 W Y position (16-bit)
VIAs
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DB00 $F0:1B00 VIA1 Internal Keyboard VIA (F256k series only!)
$DC00 $F0:1C00 VIA0 Atari joystick VIA
+0 RW IORB Port B Data
+1 RW IORA Port A Data
+2 RW DDRB Port B Data Direction Register
+3 RW DDRA Port A Data Direction Register
+4 RW T1C Timer 1 Counter (16-bit)
+6 RW T1L Timer 1 Latch (16-bit)
+8 RW T2C Timer 2 Counter (16-bit)
+A RW SDR Serial Data Registers
+B RW ACR T1_CTRL T2_CTRL SR_CTRL PBL_EN PAL_EN
+C RW PCR CB2_CTRL CB1_CTRL CA1_CTRL CA1_CTRL
+D RW IFR IRQF T1F T2F CB1F CB2F SRF CA1F CA2F
+E RW IER SET T1E T2E CB1E CB2E SRE CA1E CA2E
+F RW IORA2 Port A Data (no handshake)
SD Card Controller
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DD00 $F0:1D00 RW SPI_BUSY — — — — — SPI_CLK CS_EN
$DD01 $F0:1D01 RW SPI_DATA

SPI_CLK: 400MHz init clock when set, 12.5MHz standard clock when clear.

Integer Math Coprocessor
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DE00 $F0:1E00 RW MULU_A Multiplication A (Unsigned 16-bit)
$DE02 $F0:1E02 RW MULU_B Multiplication B (Unsigned 16-bit)
$DE04 $F0:1E04 RW DIVU_DEN Division Denominator (Unsigned 16-bit)
$DE06 $F0:1E06 RW DIVU_NUM Division Numerator (Unsigned 16-bit)
$DE08 $F0:1E08 RW ADD_A Addition A (Unsigned 32-bit)
$DE0C $F0:1E0C RW ADD_B Addition B (Unsigned 32-bit)
$DE10 $F0:1E10 RW MULU Multiplication A×B Result (Unsigned 32-bit)
$DE14 $F0:1E14 RW QUOU Quotient of Num/Den (Unsigned 16-bit)
$DE16 $F0:1E16 RW REMU Remainder of Num/Den (Unsigned 16-bit)
$DE18 $F0:1E18 RW ADD_R Addition A+B Result (Unsigned 32-bit)

Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

DMA Controller
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DF00 $F0:1F00 RW START INT_EN FILL 2D ENABLE
$DF01 $F0:1F01 W Fill data byte
$DF04 $F0:1F04 RW Source SRAM Address (24-bit)
$DF08 $F0:1F08 RW Destination SRAM Address (24-bit)
$DF0C $F0:1F0C RW Count (24-bit, not 2D mode)
RW Width (16-bit, 2D mode)
$DF0E $F0:1F0E RW Height (16-bit, 2D mode)
$DF10 $F0:1F10 RW Source stride (16-bit, 2D mode)
$DF12 $F0:1F12 RW Destination stride (16-bit, 2D mode)

IO Page 1

Text Mode Font Sets
MMU Flat R/W Name Description
$C000 - $C7FF $F0:2000 - $F0:27FF Font set 0 (256 × 8-byte chars)
$C800 - $CFFF $F0:2800 - $F0:2FFF Font set 1 (256 × 8-byte chars)

Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

Graphics CLUTS
MMU Flat R/W Name Description
$D000 - $D3FF $F0:3000 - $F0:33FF Graphics CLUT 0 (256 × BGRx)
$D400 - $D7FF $F0:3400 - $F0:37FF Graphics CLUT 1 (256 × BGRx)
$D800 - $DBFF $F0:3800 - $F0:3BFF Graphics CLUT 2 (256 × BGRx)
$DC00 - $DFFF $F0:3C00 - $F0:3FFF Graphics CLUT 3 (256 × BGRx)

IO Page 2

MMU Flat R/W Name Description
$C000 - $DFFF $F0:4000 - $F0:5FFF RW Text screen character matrix

1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.

IO Page 3

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$C000 - $DFFF $F0:6000 - $F0:7FFF RW Text screen color matrix
FG color (0-15) BG color (0-15)

Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

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