IO Pages: Difference between revisions

From F256 Foenix
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== Notes ==
== Notes ==
'''SRAM Address''': The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, Core2x has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 24-bit CPU-visible addresses.
<span id="SRAM Address>'''SRAM Address'''</span>: Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, Core2x has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 24-bit CPU-visible addresses.


'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.
'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.


'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.
<span id="BGRx>'''BGRx'''</span>: A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.


== IO Page 0 ==
== IO Page 0 ==
Line 21: Line 21:
|
|
|
|
|Blue conversion table
|Blue gamma conversion table
|-
|-
|$C400 - $C4FF
|$C400 - $C4FF
Line 27: Line 27:
|
|
|
|
|Green conversion table
|Green gamma conversion table
|-
|-
|$C800 - $C8FF
|$C800 - $C8FF
Line 33: Line 33:
|
|
|
|
|Red conversion table
|Red gamma conversion table
|}
{| class="wikitable"
|+Mouse Pointer
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
|}


Line 106: Line 120:
!Flat
!Flat
!R/W
!R/W
!Name
!7
!7
!6
!6
Line 116: Line 131:
|-
|-
|$D002
|$D002
|$F0:1002
|RW
|
|
|RW
|—
|—
| colspan="3" |Layer 1
| colspan="3" |Layer 1
Line 124: Line 140:
|-
|-
|$D003
|$D003
|$F0:1003
|RW
|
|
|RW
|—
|—
|—
|—
Line 132: Line 149:
|—
|—
| colspan="3" |Layer 2
| colspan="3" |Layer 2
|}
There are 6 configurable graphics maps that can be placed into any of the 3 visible layers. Layer 0 is the front graphics layer.
{| class="wikitable"
|+Layer Codes
!Code
!Graphics Map
|-
|0
|Bitmap 0
|-
|1
|Bitmap 1
|-
|2
|Bitmap 2
|-
|-
|
|
|
|
|-
|
|4
|Values
|Tilemap 0
| colspan="8" |0-2: Bitmap 0-2
|-
4-6: Tilemap 0-2
|5
|Tilemap 1
|-
|6
|Tilemap 2
|}
|}
{| class="wikitable"
{| class="wikitable"
Line 176: Line 173:
|-
|-
|$D004
|$D004
|
|$F0:1004
|RW
|RW
|BRDR_CTRL
|BRDR_CTRL
Line 187: Line 184:
|-
|-
|$D005
|$D005
|
|$F0:1005
|RW
|RW
|BRDR_BLUE
|BRDR_BLUE
Line 193: Line 190:
|-
|-
|$D006
|$D006
|
|$F0:1006
|RW
|RW
|BRDR_GREEN
|BRDR_GREEN
Line 199: Line 196:
|-
|-
|$D007
|$D007
|
|$F0:1007
|RW
|RW
|BRDR_RED
|BRDR_RED
Line 205: Line 202:
|-
|-
|$D008
|$D008
|
|$F0:1008
|RW
|RW
|BRDR_WIDTH
|BRDR_WIDTH
Line 214: Line 211:
|-
|-
|$D009
|$D009
|
|$F0:1009
|RW
|RW
|BRDR_HEIGHT
|BRDR_HEIGHT
Line 238: Line 235:
|-
|-
|$D00D
|$D00D
|
|$F0:100D
|RW
|RW
|BGND_BLUE
|BGND_BLUE
Line 244: Line 241:
|-
|-
|$D00E
|$D00E
|
|$F0:100E
|RW
|RW
|BGND_GREEN
|BGND_GREEN
Line 250: Line 247:
|-
|-
|$D00F
|$D00F
|
|$F0:100F
|RW
|RW
|BGND_RED
|BGND_RED
Line 271: Line 268:
|-
|-
|$D010
|$D010
|
|$F0:1010
|RW
|RW
|CCR
|CCR
Line 281: Line 278:
| colspan="2" |RATE
| colspan="2" |RATE
|ENABLE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|-
|$D012
|$D012
|
|$F0:1012
|RW
|RW
|CCH
|CCH
| colspan="8" |Cursor character code
| colspan="8" |Cursor character code
|-
|-
|$D014 - $D015
|$D014
|
|$F0:1014
|RW
|RW
|CURX
|CURX
| colspan="8" |Cursor X position (16-bit)
| colspan="8" |Cursor X position (16-bit)
|-
|-
|$D016 - $D017
|$D016
|
|$F0:1016
|RW
|RW
|CURY
|CURY
| colspan="8" |Cursor Y position (16-bit)
| colspan="8" |Cursor Y position (16-bit)
|}
{| class="wikitable"
|+Cursor Flash Rate
!Value
!Rate
|-
|0
|1 second
|-
|1
|1/2 second
|-
|2
|1/4 second
|-
|3
|1/8 second
|}
|}
{| class="wikitable"
{| class="wikitable"
Line 332: Line 321:
!0
!0
|-
|-
|$D018 - $D019
|$D018
|
|$F0:1018
|R
|R
|RAST_COL
|RAST_COL
| colspan="8" |Raster current column (12-bit)
| colspan="8" |Raster current column (12-bit)
|-
|-
|$D01A - $D01B
|$D01A
|
|$F0:101A
|R
|R
|RAST_ROW
|RAST_ROW
Line 345: Line 334:
|-
|-
|$D018
|$D018
|
|$F0:1018
|W
|W
|LINT_CTRL
|LINT_CTRL
Line 357: Line 346:
|ENABLE
|ENABLE
|-
|-
|$D019 - $D01A
|$D019
|
|$F0:1019
|W
|W
|LINT_L
|LINT_L
Line 381: Line 370:
|-
|-
|$D100
|$D100
|
|$F0:1100
|RW
|RW
|
|
Line 392: Line 381:
|ENABLE
|ENABLE
|-
|-
|$D101 - $D103
|$D101
|
|$F0:1101
|RW
|RW
|
|
| colspan="8" |SRAM Address of bitmap 0 pixels (24-bit)
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of bitmap 0 pixels (24-bit)
|-
|-
|$D108
|$D108
|
|$F0:1108
|RW
|RW
|
|
Line 410: Line 399:
|ENABLE
|ENABLE
|-
|-
|$D109 - $D10B
|$D109
|
|$F0:1109
|RW
|RW
|
|
| colspan="8" |SRAM Address of bitmap 1 pixels (24-bit)
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of bitmap 1 pixels (24-bit)
|-
|-
|$D110
|$D110
|
|$F0:1110
|RW
|RW
|
|
Line 428: Line 417:
|ENABLE
|ENABLE
|-
|-
|$D111 - $D103
|$D111
|
|$F0:1111
|RW
|RW
|
|
| colspan="8" |SRAM Address of bitmap 2 pixels (24-bit)
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of bitmap 2 pixels (24-bit)
|}
|}


Line 451: Line 440:
|-
|-
|$D200
|$D200
|
|$F0:1200
|
|
|
|
Line 457: Line 446:
|-
|-
|$D20C
|$D20C
|
|$F0:120C
|
|
|
|
Line 463: Line 452:
|-
|-
|$D218
|$D218
|
|$F0:1218
|
|
|
|
| colspan="8" |Tilemap 2
| colspan="8" |Tilemap 2
|}
{| class="wikitable"
|+Tilemap
!Offset
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$00
|
| +$00
|W
|W
|
|
Line 494: Line 470:
|ENABLE
|ENABLE
|-
|-
|$01 - $03
|
| +$01
|W
|W
|
|
| colspan="8" |SRAM Address of tile map entries (24-bit)
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit)
|-
|-
|$04
|
|W
| +$04
|W
|
|
| colspan="8" |MAP_SIZE_X (8-bit)
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|-
|$06
|
| +$06
|W
|W
|
|
| colspan="8" |MAP_SIZE_Y (8-bit)
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|-
|$08
|
| +$08
|W
|W
|
|
Line 515: Line 495:
| colspan="4" |SSX
| colspan="4" |SSX
|-
|-
|$09
|
| +$09
|W
|W
|
|
Line 522: Line 503:
| colspan="6" |X[9:4]
| colspan="6" |X[9:4]
|-
|-
|$0A
|
| +$0A
|W
|W
|
|
Line 528: Line 510:
| colspan="4" |SSY
| colspan="4" |SSY
|-
|-
|$0B
|
| +$0B
|W
|W
|
|
Line 552: Line 535:
!0
!0
|-
|-
|$D280 - $D283
|$D280
|
|$F0:1280
|
|
|
|
| colspan="8" |Tileset 0
| colspan="8" |Tileset 0
|-
|-
|$D284 - $D287
|$D284
|
|$F0:1284
|
|
|
|
| colspan="8" |Tileset 1
| colspan="8" |Tileset 1
|-
|-
|$D288 - $D28B
|$D288
|
|$F0:1288
|
|
|
|
| colspan="8" |Tileset 2
| colspan="8" |Tileset 2
|-
|-
|$D28C - $D28F
|$D28C
|
|$F0:128C
|
|
|
|
| colspan="8" |Tileset 3
| colspan="8" |Tileset 3
|-
|-
|$D290 - $D293
|$D290
|
|$F0:1290
|
|
|
|
| colspan="8" |Tileset 4
| colspan="8" |Tileset 4
|-
|-
|$D294 - $D298
|$D294
|
|$F0:1294
|
|
|
|
| colspan="8" |Tileset 5
| colspan="8" |Tileset 5
|-
|-
|$D298 - $D29B
|$D298
|
|$F0:1298
|
|
|
|
| colspan="8" |Tileset 6
| colspan="8" |Tileset 6
|-
|-
|$D29C - $D29F
|$D29C
|$F0:129C
|
|
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
|
| colspan="8" |Tileset 7
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|}
|-
{| class="wikitable"
|+Tileset
!Offset
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0 - 2
|W
|
|
| colspan="8" |SRAM Address of tile pixels (24-bit)
| +3
|-
|3
|W
|W
|
|
|
|—
|
|—
|
|—
|
|—
|SQUARE
|SQUARE
|
|—
|
|—
|
|—
|}
|}
{| class="wikitable"
{| class="wikitable"
Line 647: Line 618:
|-
|-
|$D400
|$D400
|
|$F0:1400
|
|
|
|
Line 653: Line 624:
|-
|-
|$D500
|$D500
|
|$F0:1500
|
|
|
|
| colspan="8" |Right SID
| colspan="8" |Right SID
|}
{| class="wikitable"
|+SID Registers
!Offset
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
| +$00 - $01
|
| +$00
|W
|W
|Voice 1
|Voice 1
| colspan="8" |Frequency (16-bit)
| colspan="8" |Frequency (16-bit)
|-
|-
| +$02 - $03
|
| +$02
|W
|W
|
|
| colspan="8" |Pulse width (12-bit)
| colspan="8" |Pulse width (12-bit)
|-
|-
|
| +$04
| +$04
|W
|W
Line 694: Line 654:
|GATE
|GATE
|-
|-
|
| +$05
| +$05
|W
|W
Line 703: Line 664:
|
|
|-
|-
|
| +$06
| +$06
|W
|W
Line 709: Line 671:
| colspan="4" |RELEASE
| colspan="4" |RELEASE
|-
|-
| +$07 - $08
|
| +$07
|W
|W
|Voice 2
|Voice 2
| colspan="8" |Frequency (16-bit)
| colspan="8" |Frequency (16-bit)
|-
|-
| +$09 - $0A
|
| +$09
|W
|W
|
|
| colspan="8" |Pulse width (12-bit)
| colspan="8" |Pulse width (12-bit)
|-
|-
|
| +$0B
| +$0B
|W
|W
Line 731: Line 696:
|GATE
|GATE
|-
|-
|
| +$0C
| +$0C
|W
|W
Line 740: Line 706:
|
|
|-
|-
|
| +$0D
| +$0D
|W
|W
Line 746: Line 713:
| colspan="4" |RELEASE
| colspan="4" |RELEASE
|-
|-
| +$0E - $0F
|
| +$0E
|W
|W
|Voice 3
|Voice 3
| colspan="8" |Frequency (16-bit)
| colspan="8" |Frequency (16-bit)
|-
|-
| +$10 - $11
|
| +$10
|W
|W
|
|
| colspan="8" |Pulse width (12-bit)
| colspan="8" |Pulse width (12-bit)
|-
|-
|
| +$12
| +$12
|W
|W
Line 768: Line 738:
|GATE
|GATE
|-
|-
|
| +$13
| +$13
|W
|W
Line 777: Line 748:
|
|
|-
|-
|
| +$14
| +$14
|W
|W
Line 783: Line 755:
| colspan="4" |RELEASE
| colspan="4" |RELEASE
|-
|-
|
| +$15
| +$15
|W
|W
Line 793: Line 766:
| colspan="3" |FC[2:0]
| colspan="3" |FC[2:0]
|-
|-
|
| +$16
| +$16
|W
|W
Line 798: Line 772:
| colspan="8" |FC[10:3]
| colspan="8" |FC[10:3]
|-
|-
|
| +$17
| +$17
|W
|W
Line 807: Line 782:
|FILTV1
|FILTV1
|-
|-
|
| +$18
| +$18
|W
|W
Line 832: Line 808:
|-
|-
|$D580
|$D580
|
|$F0:1580
|W
|W
|
|
Line 838: Line 814:
|-
|-
|$D581
|$D581
|
|$F0:1581
|W
|W
|
|
Line 844: Line 820:
|-
|-
|$D582
|$D582
|
|$F0:1582
|W
|W
|
|
Line 865: Line 841:
|-
|-
|$D600
|$D600
|
|$F0:1600
|
|
|
|
Line 871: Line 847:
|-
|-
|$D608
|$D608
|
|$F0:1608
|
|
|
|
Line 877: Line 853:
|-
|-
|$D610
|$D610
|
|$F0:1610
|
|
|
|
Line 899: Line 875:
|-
|-
|$D620
|$D620
|
|$F0:1620
|W
|W
|
|
Line 905: Line 881:
|-
|-
|$D621
|$D621
|
|$F0:1621
|W
|W
|
|
Line 912: Line 888:
|-
|-
|$D622
|$D622
|
|$F0:1622
|R
|R
|
|
Line 958: Line 934:
|-
|-
|$D630
|$D630
|
|$F0:1630
|R
|R
|RXD
|RXD
Line 970: Line 946:
|-
|-
|$D631
|$D631
|
|$F0:1631
|RW
|RW
|IER
|IER
Line 987: Line 963:
| colspan="9" |'''DLAB = 1'''
| colspan="9" |'''DLAB = 1'''
|-
|-
|$D630 - $D631
|$D630
|
|$F0:1630
|RW
|RW
|DL
|DL
Line 1,000: Line 976:
|-
|-
|$D632
|$D632
|
|$F0:1632
|R
|R
|IIR
|IIR
Line 1,022: Line 998:
|-
|-
|$D633
|$D633
|
|$F0:1633
|RW
|RW
|LCR
|LCR
Line 1,047: Line 1,023:
|-
|-
|$D640
|$D640
|
|$F0:1640
|RW
|RW
|PS2_CTRL
|PS2_CTRL
Line 1,060: Line 1,036:
|-
|-
|$D641
|$D641
|
|$F0:1641
|RW
|RW
|PS2_OUT
|PS2_OUT
Line 1,066: Line 1,042:
|-
|-
|$D642
|$D642
|
|$F0:1642
|R
|R
|KBD_IN
|KBD_IN
Line 1,072: Line 1,048:
|-
|-
|$D643
|$D643
|
|$F0:1643
|R
|R
|MS_IN
|MS_IN
Line 1,078: Line 1,054:
|-
|-
|$D644
|$D644
|
|$F0:1644
|R
|R
|PS2_STAT
|PS2_STAT
Line 1,106: Line 1,082:
|-
|-
|$D650
|$D650
|
|$F0:1650
|W
|W
|T0_CTR
|T0_CTR
Line 1,131: Line 1,107:
|EQ
|EQ
|-
|-
|$D651 - $D653
|$D651
|
|$F0:1651
|RW
|RW
|T0_VAL
|T0_VAL
Line 1,138: Line 1,114:
|-
|-
|$D654
|$D654
|
|$F0:1654
|RW
|RW
|T0_CMP_CTR
|T0_CMP_CTR
Line 1,150: Line 1,126:
|RECLR
|RECLR
|-
|-
|$D655 - $D657
|$D655
|
|$F0:1655
|RW
|RW
|T0_CMP
|T0_CMP
Line 1,170: Line 1,146:
|-
|-
|$D658
|$D658
|
|$F0:1658
|W
|W
|T1_CTR
|T1_CTR
Line 1,195: Line 1,171:
|EQ
|EQ
|-
|-
|$D659 - $D65B
|$D659
|
|$F0:1659
|RW
|RW
|T1_VAL
|T1_VAL
Line 1,202: Line 1,178:
|-
|-
|$D65C
|$D65C
|
|$F0:165C
|RW
|RW
|T1_CMP_CTR
|T1_CMP_CTR
Line 1,214: Line 1,190:
|RECLR
|RECLR
|-
|-
|$D65D - $D65F
|$D65D
|
|$F0:165D
|RW
|RW
|T1_CMP
|T1_CMP
Line 1,221: Line 1,197:
|}
|}
{| class="wikitable"
{| class="wikitable"
|+RTC Registers
|+Interrupt Registers
!MMU
!MMU
!Flat
!Flat
Line 1,235: Line 1,211:
!0
!0
|-
|-
|$D690
|$D660
|
|
|
|RW
|INT_PENDING
|Seconds
| colspan="8" |Per-interrupt flags (24-bit)
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|-
|$D691
|$D664
|
|
|
|RW
|INT_POLARITY
|Seconds Alarm
| colspan="8" |Per-interrupt flags (24-bit)
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|-
|$D692
|$D668
|
|
|
|RW
|INT_EDGE
|Minutes
| colspan="8" |Per-interrupt flags (24-bit)
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|-
|$D693
|$D66C
|
|
|
|RW
|INT_MASK
|Minutes Alarm
| colspan="8" |Per-interrupt flags (24-bit)
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|-
|$D694
|
|
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|
|
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|
|
|RW
|
|Days
|
|
|
|
|
|
|
|
|}
{| class="wikitable"
|+Interrupt flags
!Offset
!Mask
!Name
!Description
|-
|0
|0
|$01
|INT_VKY_SOF
|Start of Frame interrupt (beginning of VSYNC)
|-
|0
|0
| colspan="2" |10s digit
|$02
| colspan="4" |1s digit
|INT_VKY_SOL
|Start of Line interrupt
|-
|-
|$D697
|
|RW
|Days Alarm
|0
|0
|$04
|INT_PS2_KBD
|PS/2 keyboard event
|-
|0
|0
| colspan="2" |10s digit
|$08
| colspan="4" |1s digit
|INT_PS2_MOUSE
|PS/2 mouse event
|-
|-
|$D698
|
|RW
|Day of Week
|0
|0
|0
|0
|$10
|INT_TIMER_0
|TIMER0 has reached its target value
|-
|0
|0
|$20
|INT_TIMER_1
|TIMER1 has reached its target value
|-
|0
|0
| colspan="3" |1s digit
|$80
|INT_CARTRIDGE
|Interrupt asserted from cartridge port
|-
|-
|$D699
|
|
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|
|
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|
|
|RW
|
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|-
|$D69C
|1
|
|$01
|RW
|INT_UART
|Enables
|The UART is ready to receive or send data
|0
|-
|0
|1
|0
|$10
|0
|INT_RTC
|AIE
|Interrupt from real time clock chip
|PIE
|-
|PWRIE
|1
|ABE
|$20
|INT_VIA0
|Event from the joystick VIA chip
|-
|1
|$40
|INT_VIA1
|Event from the keyboard VIA chip (F256k Series Only!)
|-
|1
|$80
|INT_SDC_INS
|SD Card has been inserted
|-
|-
|$D69D
|
|
|RW
|
|Flags
|
|0
|
|0
|-
|0
|2
|0
|$01
|AF
|IEC_DATA_i
|PF
|IEC data in
|PWRF
|BVF
|-
|-
|$D69E
|2
|
|$02
|RW
|IEC_CLK_i
|Control
|IEC clock in
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|-
|$D69F
|2
|
|$04
|RW
|IEC_ATN_i
|Century
|IEC attention in
| colspan="4" |10s digit
|-
| colspan="4" |1s digit
|2
|$08
|IEC_SREQ_i
|IEC service request in
|}
|}
{| class="wikitable"
{| class="wikitable"
|+Text mode CLUT
|+DIP Switches
!MMU
!MMU
!Flat
!Flat
Line 1,400: Line 1,360:
!0
!0
|-
|-
|$D800 - $D83F
|$D670
|
|
|W
|R
|
|
| colspan="8" |Text foreground colors (16 × BGRx)
|GAMMA
|-
|USER2
|$D840 - $D87F
|USER1
|
|USER0
|W
| colspan="4" |BOOT
|
| colspan="8" |Text background colors (16 × BGRx)
|}
|}
{| class="wikitable"
{| class="wikitable"
|+Integer Math Coprocessor
|+IEC Registers
!MMU
!MMU
!Flat
!Flat
!R/W
!R/W
!Name
!Name
!7
!7
!6
!6
!5
!5
!4
!4
!3
!3
!2
!2
!1
!1
!0
!0
|-
|-
|$DE00 - $DE01
|$D680
|
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}
{| class="wikitable"
|+RTC Registers
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}
{| class="wikitable"
|+System Control Registers
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|
|W
|SYS0
|RESET
|—
|CAP_EN
|BUZZ
|L1
|L0
|SD_L
|PWR_L
|-
|
|
|R
|
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_L
|PWR_L
|-
|$D6A1
|
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MN
|L0_MN
|}
{| class="wikitable"
|+F256k Series LEDs
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7 - $D6A9
|
|W
|
| colspan="8" |Power LED color (BGR)
|-
|$D6AA - $D6AC
|
|W
|
| colspan="8" |Media LED color (BGR)
|-
|$D6AD - $D6AF
|
|W
|
| colspan="8" |Shift LED color (BGR)
|}
{| class="wikitable"
|+Machine ID and FPGA Core Versions
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|
|R
|MID
|—
|—
|—
| colspan="5" |ID
|-
|$D6A8
|
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}
{| class="wikitable"
|+Mouse Pointer Control
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|
|W
|
| colspan="8" |PS2_BYTE_2
|}
{| class="wikitable"
|+PCB Information
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}
{| class="wikitable"
|+Text mode CLUT
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}
{| class="wikitable"
|+Sprite Registers
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32, 1: 24×24, 2: 16×16, 3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}
{| class="wikitable"
|+VIAs
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00
|
|
|VIA1
| colspan="8" |Internal Keyboard VIA (F256k series only!)
|-
|$DC00
|
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+SD Card Controller
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|$DD01
|
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.
{| class="wikitable"
|+Integer Math Coprocessor
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00 - $DE01
|
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE00 - $DE02
|
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04 - $DE05
|
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06 - $DE07
|
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08 - $DE0B
|
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C - $DE0F
|
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10 - $DE13
|
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14 - $DE15
|
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16 - $DE17
|
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18 - $DE1B
|
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.
{| class="wikitable"
|+DMA Controller
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|
|RW
|
|START
|
|
|
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|
|W
|
| colspan="8" |Fill data byte
|-
|$DF04
|
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|
|RW
|
|
|RW
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|-
|$DE00 - $DE02
|$DF0C
|
|
|RW
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04 - $DE05
|
|
|RW
| colspan="8" |Count (24-bit, not 2D mode)
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|-
|$DE06 - $DE07
|$DF0C
|
|
|RW
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08 - $DE0B
|
|
|RW
| colspan="8" |Width (16-bit, 2D mode)
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|-
|$DE0C - $DE0F
|$DF0E
|
|
|RW
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
|
| colspan="8" |
| colspan="8" |Height (16-bit, 2D mode)
|-
|-
|$DE10 - $DE13
|$DF10
|
|
|RW
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14 - $DE15
|
|
|RW
| colspan="8" |Source stride (16-bit, 2D mode)
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|-
|$DE16 - $DE17
|$DF12
|
|
|RW
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18 - $DE1B
|
|
|RW
| colspan="8" |Destination stride (16-bit, 2D mode)
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.


== IO Page 1 ==
== IO Page 1 ==
Line 1,529: Line 2,254:
|
|
|
|
|Graphics CLUT 0 (256 × BGRx)
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|-
|$D400 - $D7FF
|$D400 - $D7FF
Line 1,535: Line 2,260:
|
|
|
|
|Graphics CLUT 1 (256 × BGRx)
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|-
|$D800 - $DBFF
|$D800 - $DBFF
Line 1,541: Line 2,266:
|
|
|
|
|Graphics CLUT 2 (256 × BGRx)
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|-
|$DC00 - $DFFF
|$DC00 - $DFFF
Line 1,547: Line 2,272:
|
|
|
|
|Graphics CLUT 3 (256 × BGRx)
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
|}
== IO Page 2 ==
== IO Page 2 ==

Revision as of 12:16, 9 October 2025

More detailed information is found in the Manuals.

Notes

SRAM Address: Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, Core2x has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 24-bit CPU-visible addresses.

Model names: Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

BGRx: A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

IO Page 0

Gamma Lookup
MMU Flat R/W Name Description
$C000 - $C0FF $F0:0000 - $F0:00FF Blue gamma conversion table
$C400 - $C4FF $F0:0400 - $F0:04FF Green gamma conversion table
$C800 - $C8FF $F0:0800 - $F0:08FF Red gamma conversion table
Mouse Pointer
MMU Flat R/W Name Description
$CC00 - $CCFF $F0:0C00 - $F0:0CFF Mouse pointer bitmap (16×16 greyscale bytes)

Master Control Registers ($D0xx, $F0:10xx)

Master Control
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D000 $F0:1000 RW MSTR_CTRL_0 — GAMMA SPRITE TILE BITMAP GRAPH OVRLY TEXT
$D001 $F0:1001 RW MSTR_CTRL_1 — — FON_SET FON_OVLY MON_SLP DBL_Y DBL_X CLK_70

TEXT: Enable text layer

OVRLY: Overlay text on graphics, by making text background transparent. See FON_OVLY

GRAPH: Enable graphics layers (tile, sprites, bitmaps)

BITMAP: Enable bitmap layers (if GRAPH is also set)

TILE: Enable tile layers (if GRAPH is also set)

SPRITE: Enable sprite layers (if GRAPH is also set)

GAMMA: Enable gamma correction

CLK_70: Enable 400p70, else 480p60

DBL_X, DBL_Y: Double text mode character width & height

MON_SLP: Turn off monitor SYNC, putting it into sleep mode

FON_OVLY: Only BG color 0 is transparent in OVRLY mode. Else, all BG colors are transparent.

FON_SET: Chooses font set 0 or 1

Layer Configuration
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D002 $F0:1002 RW — Layer 1 — Layer 0
$D003 $F0:1003 RW — — — — — Layer 2
Values 0-2: Bitmap 0-2

4-6: Tilemap 0-2

Border
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D004 $F0:1004 RW BRDR_CTRL — SCROLL_X — — — ENABLE
$D005 $F0:1005 RW BRDR_BLUE Border color Blue component
$D006 $F0:1006 RW BRDR_GREEN Border color Green component
$D007 $F0:1007 RW BRDR_RED Border color Red component
$D008 $F0:1008 RW BRDR_WIDTH — — — SIZE_X
$D009 $F0:1009 RW BRDR_HEIGHT — — — SIZE_Y
Background Color
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D00D $F0:100D RW BGND_BLUE Background color Blue component
$D00E $F0:100E RW BGND_GREEN Background color Green component
$D00F $F0:100F RW BGND_RED Background color Red component
Text Cursor
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D010 $F0:1010 RW CCR FLASH_DIS RATE ENABLE
RATE 0: 1 second

1: 1/2 second 2: 1/4 second 3: 1/8 second

$D012 $F0:1012 RW CCH Cursor character code
$D014 $F0:1014 RW CURX Cursor X position (16-bit)
$D016 $F0:1016 RW CURY Cursor Y position (16-bit)
Raster
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D018 $F0:1018 R RAST_COL Raster current column (12-bit)
$D01A $F0:101A R RAST_ROW Raster current row (12-bit)
$D018 $F0:1018 W LINT_CTRL ENABLE
$D019 $F0:1019 W LINT_L Line interrupt line (12-bit)

Bitmap Control Registers ($D1xx, $F0:11xx)

Bitmaps
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D100 $F0:1100 RW CLUT ENABLE
$D101 $F0:1101 RW SRAM Address of bitmap 0 pixels (24-bit)
$D108 $F0:1108 RW CLUT ENABLE
$D109 $F0:1109 RW SRAM Address of bitmap 1 pixels (24-bit)
$D110 $F0:1110 RW CLUT ENABLE
$D111 $F0:1111 RW SRAM Address of bitmap 2 pixels (24-bit)

Tilemap Control Registers ($D2xx, $F0:12xx)

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D200 $F0:1200 Tilemap 0
$D20C $F0:120C Tilemap 1
$D218 $F0:1218 Tilemap 2
+$00 W TILE_SIZE_8 ENABLE
+$01 W SRAM Address of tile map entries (24-bit)
+$04 W MAP_SIZE_X (8-bit)
+$06 W MAP_SIZE_Y (8-bit)
+$08 W X[3:0] SSX
+$09 W — — X[9:4]
+$0A W Y[3:0] SSY
+$0B W — — — — Y[7:4]
Tilesets
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D280 $F0:1280 Tileset 0
$D284 $F0:1284 Tileset 1
$D288 $F0:1288 Tileset 2
$D28C $F0:128C Tileset 3
$D290 $F0:1290 Tileset 4
$D294 $F0:1294 Tileset 5
$D298 $F0:1298 Tileset 6
$D29C $F0:129C Tileset 7
+0 W SRAM Address of tile pixels (24-bit)
+3 W — — — — SQUARE — — —
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D400 $F0:1400 Left SID
$D500 $F0:1500 Right SID
+$00 W Voice 1 Frequency (16-bit)
+$02 W Pulse width (12-bit)
+$04 W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$05 W ATTACK DELAY
+$06 W SUSTAIN RELEASE
+$07 W Voice 2 Frequency (16-bit)
+$09 W Pulse width (12-bit)
+$0B W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$0C W ATTACK DELAY
+$0D W SUSTAIN RELEASE
+$0E W Voice 3 Frequency (16-bit)
+$10 W Pulse width (12-bit)
+$12 W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$13 W ATTACK DELAY
+$14 W SUSTAIN RELEASE
+$15 W Misc — — — — — FC[2:0]
+$16 W FC[10:3]
+$17 W RESONANCE EXT FILTV3 FILTV2 FILTV1
+$18 W MUTEV3 HIGH BAND LOW VOLUME
OPL3 Registers (NOT ON F256JR)
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D580 $F0:1580 W Address registers for ports $000 - $0FF
$D581 $F0:1581 W Data registers for all ports
$D582 $F0:1582 W Address register for ports $100 - $1FF
PSG Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D600 $F0:1600 PSG Left
$D608 $F0:1608 PSG Left + Right
$D610 $F0:1610 PSG Right

Note the stereo separation is controlled with the PSG_ST flag.

CODEC Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D620 $F0:1620 W DATA[7:0]
$D621 $F0:1621 W REGISTER DATA[8]
$D622 $F0:1622 R — — — — — — — BUSY
W — — — — — — — START
UART Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
DLAB = 0
$D630 $F0:1630 R RXD RX_DATA
W TXR TX_DATA
$D631 $F0:1631 RW IER — — — — STAT ERR TXE RXA
DLAB = 1
$D630 $F0:1630 RW DL DIV (16-bit)
$D632 $F0:1632 R IIR FIFO FIFO64 — STATE /PENDING
W FCR RXT FIFO64 — DMA TXR RXR FIFOE
$D633 $F0:1633 RW LCR DLAB — PARITY STOP DATA
PS/2 Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D640 $F0:1640 RW PS2_CTRL — — MCLR KCLR M_WR — K_WR —
$D641 $F0:1641 RW PS2_OUT Data to keyboard
$D642 $F0:1642 R KBD_IN Data in from keyboard FIFO
$D643 $F0:1643 R MS_IN Data in from mouse FIFO
$D644 $F0:1644 R PS2_STAT K_AK K_NK M_AK M_NK — — MEMP KEMP
Timer Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D650 $F0:1650 W T0_CTR — — — — UP LD CLR EN
R T0_STAT — — — — — — — EQ
$D651 $F0:1651 RW T0_VAL VAL (24-bit)
$D654 $F0:1654 RW T0_CMP_CTR — — — — — — RELD RECLR
$D655 $F0:1655 RW T0_CMP CMP (24-bit)
$D658 $F0:1658 W T1_CTR — — — — UP LD CLR EN
R T1_STAT — — — — — — — EQ
$D659 $F0:1659 RW T1_VAL VAL (24-bit)
$D65C $F0:165C RW T1_CMP_CTR — — — — — — RELD RECLR
$D65D $F0:165D RW T1_CMP CMP (24-bit)
Interrupt Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D660 INT_PENDING Per-interrupt flags (24-bit)
$D664 INT_POLARITY Per-interrupt flags (24-bit)
$D668 INT_EDGE Per-interrupt flags (24-bit)
$D66C INT_MASK Per-interrupt flags (24-bit)
Interrupt flags
Offset Mask Name Description
0 $01 INT_VKY_SOF Start of Frame interrupt (beginning of VSYNC)
0 $02 INT_VKY_SOL Start of Line interrupt
0 $04 INT_PS2_KBD PS/2 keyboard event
0 $08 INT_PS2_MOUSE PS/2 mouse event
0 $10 INT_TIMER_0 TIMER0 has reached its target value
0 $20 INT_TIMER_1 TIMER1 has reached its target value
0 $80 INT_CARTRIDGE Interrupt asserted from cartridge port
1 $01 INT_UART The UART is ready to receive or send data
1 $10 INT_RTC Interrupt from real time clock chip
1 $20 INT_VIA0 Event from the joystick VIA chip
1 $40 INT_VIA1 Event from the keyboard VIA chip (F256k Series Only!)
1 $80 INT_SDC_INS SD Card has been inserted
2 $01 IEC_DATA_i IEC data in
2 $02 IEC_CLK_i IEC clock in
2 $04 IEC_ATN_i IEC attention in
2 $08 IEC_SREQ_i IEC service request in
DIP Switches
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D670 R GAMMA USER2 USER1 USER0 BOOT
IEC Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D680 R IEC_I SRQ_i — — ATN_i — — CLK_i DAT_i
$D681 RW IEC_O SRQ_o RST_o NMI_EN ATN_o — — CLK_o DAT_o
RTC Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D690 RW Seconds 0 10s digit 1s digit
$D691 RW Seconds Alarm 0 10s digit 1s digit
$D692 RW Minutes 0 10s digit 1s digit
$D693 RW Minutes Alarm 0 10s digit 1s digit
$D694 RW Hours AM/PM 0 10s digit 1s digit
$D695 RW Hours Alarm AM/PM 0 10s digit 1s digit
$D696 RW Days 0 0 10s digit 1s digit
$D697 RW Days Alarm 0 0 10s digit 1s digit
$D698 RW Day of Week 0 0 0 0 0 1s digit
$D699 RW Month 0 0 0 10s digit 1s digit
$D69A RW Year 10s digit 1s digit
$D69B RW Rates 0 WD RS
$D69C RW Enables 0 0 0 0 AIE PIE PWRIE ABE
$D69D RW Flags 0 0 0 0 AF PF PWRF BVF
$D69E RW Control 0 0 0 0 UTI STOP 12/24 DSE
$D69F RW Century 10s digit 1s digit
System Control Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6A0 W SYS0 RESET — CAP_EN BUZZ L1 L0 SD_L PWR_L
R — SD_WP SD_CD BUZZ L1 L0 SD_L PWR_L
$D6A1 RW SYS1 L1_RATE L0_RATE SID_ST PSG_ST L1_MN L0_MN
F256k Series LEDs
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6A7 - $D6A9 W Power LED color (BGR)
$D6AA - $D6AC W Media LED color (BGR)
$D6AD - $D6AF W Shift LED color (BGR)
Machine ID and FPGA Core Versions
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6A7 R MID — — — ID
$D6A8 R PCBID0 ASCII character 0: "B" (See also $D6EB)
$D6A9 R PCBID1 ASCII character 1: "0"
$D6AA R CHSV VICKY sub-version in BCD (16-bit)
$D6AC R CHV VICKY version in BCD (16-bit)
$D6AE R CHN VICKY number in BCD (16-bit)
Mouse Pointer Control
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6E0 W — — — — — — MODE EN
$D6E2 RW X (16-bit)
$D6E4 RW Y (16-bit)
$D6E6 W PS2_BYTE_0
$D6E7 W PS2_BYTE_1
$D6E8 W PS2_BYTE_2
PCB Information
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6EB R PCBMA PCB Major Rev (ASCII)
$D6EC R PCBMI PCB Minor Rev (ASCII)
$D6ED R PCBD PCB Day (BCD)
$D6EE R PCBM PCB Month (BCD)
$D6EF R PCBY PCB Year (BCD)
Text mode CLUT
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D800 - $D83F W Text foreground colors (16 × BGRx)
$D840 - $D87F W Text background colors (16 × BGRx)
Sprite Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D900 - $DAFF 64 × 8-byte Sprite Registers
+0 W — SIZE LAYER LUT ENABLE
SIZE 0: 32×32, 1: 24×24, 2: 16×16, 3: 8×8
+1 W SRAM Address of sprite pixels (24-bit)
+4 W X position (16-bit)
+6 W Y position (16-bit)
VIAs
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DB00 VIA1 Internal Keyboard VIA (F256k series only!)
$DC00 VIA0 Atari joystick VIA
+0 RW IORB Port B Data
+1 RW IORA Port A Data
+2 RW DDRB Port B Data Direction Register
+3 RW DDRA Port A Data Direction Register
+4 RW T1C Timer 1 Counter (16-bit)
+6 RW T1L Timer 1 Latch (16-bit)
+8 RW T2C Timer 2 Counter (16-bit)
+A RW SDR Serial Data Registers
+B RW ACR T1_CTRL T2_CTRL SR_CTRL PBL_EN PAL_EN
+C RW PCR CB2_CTRL CB1_CTRL CA1_CTRL CA1_CTRL
+D RW IFR IRQF T1F T2F CB1F CB2F SRF CA1F CA2F
+E RW IER SET T1E T2E CB1E CB2E SRE CA1E CA2E
+F RW IORA2 Port A Data (no handshake)
SD Card Controller
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DD00 RW SPI_BUSY — — — — — SPI_CLK CS_EN
$DD01 RW SPI_DATA

SPI_CLK: 400MHz init clock when set, 12.5MHz standard clock when clear.

Integer Math Coprocessor
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DE00 - $DE01 RW MULU_A Multiplication A (Unsigned 16-bit)
$DE00 - $DE02 RW MULU_B Multiplication B (Unsigned 16-bit)
$DE04 - $DE05 RW DIVU_DEN Division Denominator (Unsigned 16-bit)
$DE06 - $DE07 RW DIVU_NUM Division Numerator (Unsigned 16-bit)
$DE08 - $DE0B RW ADD_A Addition A (Unsigned 32-bit)
$DE0C - $DE0F RW ADD_B Addition B (Unsigned 32-bit)
$DE10 - $DE13 RW MULU Multiplication A×B Result (Unsigned 32-bit)
$DE14 - $DE15 RW QUOU Quotient of Num/Den (Unsigned 16-bit)
$DE16 - $DE17 RW REMU Remainder of Num/Den (Unsigned 16-bit)
$DE18 - $DE1B RW ADD_R Addition A+B Result (Unsigned 32-bit)

Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

DMA Controller
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DF00 RW START INT_EN FILL 2D ENABLE
$DF01 W Fill data byte
$DF04 RW Source SRAM Address (24-bit)
$DF08 RW Destination SRAM Address (24-bit)
$DF0C RW Count (24-bit, not 2D mode)
$DF0C RW Width (16-bit, 2D mode)
$DF0E RW Height (16-bit, 2D mode)
$DF10 RW Source stride (16-bit, 2D mode)
$DF12 RW Destination stride (16-bit, 2D mode)

IO Page 1

Text Mode Font Sets
MMU Flat R/W Name Description
$C000 - $C7FF $F0:2000 - $F0:27FF Font set 0 (256 × 8-byte chars)
$C800 - $CFFF $F0:2800 - $F0:2FFF Font set 1 (256 × 8-byte chars)

Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

Graphics CLUTS
MMU Flat R/W Name Description
$D000 - $D3FF $F0:3000 - $F0:33FF Graphics CLUT 0 (256 × BGRx)
$D400 - $D7FF $F0:3400 - $F0:37FF Graphics CLUT 1 (256 × BGRx)
$D800 - $DBFF $F0:3800 - $F0:3BFF Graphics CLUT 2 (256 × BGRx)
$DC00 - $DFFF $F0:3C00 - $F0:3FFF Graphics CLUT 3 (256 × BGRx)

IO Page 2

MMU Flat R/W Name Description
$C000 - $DFFF $F0:4000 - $F0:5FFF RW Text screen character matrix

1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.

IO Page 3

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$C000 - $DFFF $F0:6000 - $F0:7FFF RW Text screen color matrix
FG color (0-15) BG color (0-15)

Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

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