FPU Accumulator
This design for a better FPU block for 8/16 bit access, which also integrates 32-bit integer processing. While it's 32 bits, copying around 32-bit values with the CPU is mostly avoided.
There are 256 32-bit registers (TBD- RAM or FPGA registers. Former allows swapping in new sets) and one 32-bit accumulator. Any of these can hold useful constants (including 0, 1, etc) for reference. It's similar to the 6502 accumulator and zeropage values.
Commands are issued by writing a byte to an I/O location. The location identifies the command, and the byte written is often a selector for which register number to use, sometimes a literal integer value, or ignored.
Status bits (TBD) are available to read, with various errors, and Z/N/V/C flags just like the 6502.
Set the integer fixed point location (TBD) which affects multiply, divide, and conversion with floats.
TODO - should there be separate signed & unsigned variants of integer operations (including F2I), or a mode bit for signedness?
| Cmd # | Name | Parameter | Description |
|---|---|---|---|
| LOAD | Reg | A = Reg | |
| STORE | Reg | Reg = A | |
| SWAP | Reg | (A, Reg) = (Reg, A) |
| Cmd # | Name | Parameter | Description |
|---|---|---|---|
| FADD | Reg | A = A + Reg | |
| FSUB | Reg | A = A - Reg | |
| FRSUB | Reg | A = Reg - A | |
| FMUL | Reg | A = A * Reg | |
| FDIV | Reg | A = A / Reg | |
| FRDIV | Reg | A = Reg / A | |
| F2I | Signed flag | A = Int(A) or UInt(A) | |
| FMIN | Reg | A = Min(A, Reg) | |
| FMAX | Reg | A = Max(A, Reg) | |
| Maybe | |||
| FADDB | Byte | A = A + Val | |
| FSUBB | Byte | A = A - Val | |
| FMULB | Byte | A = A * Val | |
| FDIVB | Byte | A = A / Val | |
| FCLR | Ignored | A = 0.0 (LOAD instead) | |
| FNEG | 0 | A = -A (FRSUB instead) | |
| Cmd # | Name | Parameter | Description |
|---|---|---|---|
| IADD | Reg | A = A + Reg | |
| IADDC | Reg | A = A + Reg + C | |
| ISUB | Reg | A = A - Reg | |
| ISUBC | Reg | A = A - Reg - !C | |
| IRSUB | Reg | A = Reg - A | |
| IMUL | Reg | A = A * Reg | |
| IDIV | Reg | A = A / Reg | |
| IMOD | Reg | A = A % Reg | |
| ICMP | Reg | Status = A - Reg | |
| INEG | 0 | A = -A | |
| IAND | Reg | A = A & Reg | |
| IOR | Reg | A = A | Reg | |
| IXOR | Reg | A = A ^ Reg | |
| I2F | Signed Flag | A = Float(Int(A)) or Float(UInt(A)) | |
| ISHL | Count | A = A << Value | |
| ISHR | Count | A = A >> Value | |
| ISSHR | Count | A = A >>(signed) Value | |
| IROLL | Count | A = (A << Count) | (A >> (32 - Count)) | |
| IUMIN | Reg | A = Min(A, Reg) | |
| ISMIN | Reg | A = Min(A, Reg) | |
| IUMAX | Reg | A = Max(A, Reg) | |
| ISMAX | Reg | A = Max(A, Reg) |
