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Memory Management
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=== Memory Management Unit (MMU) === While the address bus is generally 21 bits wide, the CPU address bus of the 65c02 and the FNX6809 is only 16 bits wide. Even though the 65816 does have a 24 bit wide address bus, it is currently not used. However, this might change with a future update. To allow the addressing of the whole address space, 4 Memory Management Units (MMU) are provided, that translate the CPU logical address space to physical addresses. To achieve this, each MMU has 8 <em>slots</em>, each representing an 8 KB block of the CPU addressable memory space. The physical address space is also divided into 8 KB blocks, dividing the available 2 MB into 256 blocks. To <em>map</em> a block of physical addresses into CPU address space, the block number is written into the according slot register of the MMU. {| class="wikitable" !Slot!!CPU Address Space!!Slot Register Address |- |0||$0000 - $1FFF|| $0008 |- |1||$2000 - $3FFF|| $0009 |- |2||$4000 - $5FFF|| $000A |- |3||$6000 - $7FFF|| $000B |- |4||$8000 - $9FFF|| $000C |- |5||$A000 - $BFFF|| $000D |- |6||$C000 - $DFFF|| $000E |- |7||$E000 - $FFFF|| $000F |} Only one MMU is active at any one time. To select the active MMU, the lower two bits of address $0000 (MMU_MEM_CTRL) are used. Editing of MMUs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which set of MMU registers is to be edited, while bit 7 has to be set to 1 to enable editing. When editing is enable, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
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