Editing Hardware (section)

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion.  It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.  

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal.  For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins.  Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.  

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate. 
  
Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side.  Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side.  So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!). 

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;" 
| 
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;" 
| 
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;" 
| 
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;" 
| 
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;" 
| 
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;" 
| 
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;" 
| 
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;" 
| 
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;" 
| 
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;" 
| 
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;" 
| 
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;" 
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;" 
| 
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;" 
| 
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;" 
| 
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;" 
| 
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;" 
| 
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;" 
| 
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;" 
| 
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output
|}