Editing FPGA Releases

=== Important: ===
Most users will want to consume the "Firmware package relases" (taken from here: https://github.com/FoenixRetro/f256-firmware/releases. )  which contain both the latest of the FPGA releases seen here on this page, and the kernel/base programs intended for the flash memory. The page you're ready here is meant for power user who would want to test back compatibility or attempt some roll-backs in case bugs are found, and for readers who want to learn about the release notes of each new FPGA version.

== F256K FPGA Releases ==

=== Current F256K Release ===

{| class="wikitable"
! Series !! Version 
!Code!! Date !! Download !! Release Notes
|-
| style="white-space:nowrap;"| F256K
| style="white-space:nowrap;"| Release Candidate 14
|00140000 B0
| style="white-space:nowrap;" | 23-Dec-2023 
| style="white-space:nowrap;" | [https://ptb.discord.com/channels/691915291721990194/1054250189675843736/1188628633502359602 F256K_WBh_Dec23rd_RevB0x_RC14_0000.jic]
|Fixes a problem with the tiles; needed to be shifted by one towards the left.
|}

=== Previous F256K Releases ===

{| class="wikitable"
! Series !! Version 
!Code!! Date !! Download !! Release Notes
|-
|F256K
|Release Candidate 13
|00130000 B0
|09-Dec-2023
|[https://cdn.discordapp.com/attachments/1054250189675843736/1182993744044249149/F256K_WBh_Dec9th_RevB0x_RC13_0000.jic F256K_WBh_Dec9th_RevB0x_RC13_0000.jic]
|
* Fixes a problem with Interrupt from timer0 that was working on the Jr.
* Resolves a discrepancy between the F256Jr interrupt block and the F256K.
|-
| style="white-space:nowrap;"| F256K
| style="white-space:nowrap;"| Release Candidate 12
|00120011 B0
| style="white-space:nowrap;" | 19-Nov-2023 
| style="white-space:nowrap;"| [https://cdn.discordapp.com/attachments/1054250189675843736/1175965530000212048/F256K_WBh_Nov19th_RevB0x_RC12_0011.jic F256K_WBh_Nov19th_RevB0x_RC12_0011.jic]
| 
Corrects the issue with no-response from command $20 & $21 (not being processed in the early parser).
The Jr doesn't have the issue.
|}

== F256Jr FPGA Releases ==

=== Current F256Jr Release ===

{| class="wikitable"
! Series !! Version 
!Code!! Date !! Download !! Release Notes
|-
| style="white-space:nowrap;"| F256Jr
| style="white-space:nowrap;"| Release Candidate 18
|00180100 B0
| style="white-space:nowrap;" | 23-Dec-2023 
| style="white-space:nowrap;"| [https://cdn.discordapp.com/attachments/1010352563406770217/1188629310081347584/F256M_Wbh_Dec23rd_2023_RC18_0100.jic?ex=659b384f&is=6588c34f&hm=e38627d1334595c2bae737ba996c398b5d748a979624b79005cb720664453111& F256M_Wbh_Dec23rd_2023_RC18_0100.jic]
|Fixes a problem with the tiles; needed to be shifted by one towards the left. (0100 = Serial RAM/Flash Select)
|}

=== Previous F256Jr Releases ===

{| class="wikitable"
! Series !! Version 
!Code!! Date !! Download !! Release Notes
|-
|F256Jr
|Release Candidate 17
|?
|18-Nov-2023
|[https://cdn.discordapp.com/attachments/1010352563406770217/1175321652859523123/F256M_Wbh_Nov18th_2023_RC17_0100.jic F256M_Wbh_Nov18th_2023_RC17_0100.jic]
|In light of decision to dump the big ticket items and the accessories from the store...
* Removed the very SPI core introduced yesterday to drive the FNXNET51 module.
* Removed the DP memory for the MMU and replace it back with simple Registers, which means that when you reset the system, the MMU, Page0 will be reset back to the way it was. However, the caveat is that if you change between RAM to FLASH MMU default value, you need to do a reset, either a debug reset or General Reset because the MMU is now only 32bytes in Size, so, 4 pages of 8 values.
|-
| style="white-space:nowrap;"| F256Jr
| style="white-space:nowrap;"| Release Candidate 16
|?
| style="white-space:nowrap;" | 17-Nov-2023 
| style="white-space:nowrap;"| [https://cdn.discordapp.com/attachments/1010352563406770217/1174998797991022632/F256M_WBh_Nov17th_2023_RC16_0111.jic F256M_WBh_Nov17th_2023_RC16_0111.jic]
| 
* No Write Allowed when Debug Port writes in the MMU Memory Zone
* Incorporation of a new SPI Controller to interface with the FNXNET51 module using the NES/SNES MiniDin9 Connector
* ReSync of the Debug Generated RDY to stop the CPU. (untested)
|}

== FPGA Upgrade Guide ==

If you haven’t upgraded FPGAs before, below are some great videos to guide you.

You will need to download Quartus Prime Lite 18.1 Edition, since you are going to target a EP4CE15 FPGA (Cyclone 4).

Do not update to the latest version of Quartus Prime Lite, as the latest version doesn’t support that family of FPGA anymore and the software is very big.

Also, one might want to download only the "Intel® Quartus® Prime Programmer and Tools" as opposed to download the whole software by clicking on "Additional Software"

[https://www.intel.com/content/www/us/en/software-kit/665990/intel-quartus-prime-lite-edition-design-software-version-18-1-for-windows.html Intel Quartus Prime Lite Edition 18.1 for  Windows]

[https://www.intel.com/content/www/us/en/software-kit/665988/intel-quartus-prime-lite-edition-design-software-version-18-1-for-linux.html Intel Quartus Prime Lite Edition 18.1 for Linux]

=== Video Guide ===

Note that the below Video Guide applies to both the F256K & F256Jr, despite it just being titled F256K.

==== How to Upgrade the F256K FPGA (and F256Jr) ====

<youtube>U7bq7t_qjxg</youtube>

=== Suggested USB Blaster ===

Earth People Technology
[https://www.amazon.ca/JTAG-Blaster-Intel-Altera-Programmer/dp/B07BZMSZ3G/ref=sr_1_3?crid=WWV8P0OHVCE3&keywords=altera+usb+blaster&qid=1688067039&sprefix=altera+usb+blaster%2Caps%2C113&sr=8-3]
[https://earthpeopletechnology.com/?wpsc-product=ept-2232h-sp-s1]

Terasic USB Blaster (low cost version)
[https://www.digikey.ca/en/products/detail/terasic-inc/P0302/2003484]
[https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=&No=46#contents]

Chinese Knockoff (please avoid if possible)

=== Open Source blaster software ===

For those who are struggling to program the FPGA with Linux or Apple, Stef found this great tool:

https://github.com/trabucayre/openFPGALoader/releases