FPGA Releases

1. move the FG & BG Text LUT to:

Important:

Most users will want to consume the "Firmware package relases" (taken from here: https://github.com/FoenixRetro/f256-firmware/releases. ) which contain both the latest of the FPGA releases seen here on this page, and the kernel/base programs intended for the flash memory. The page you're ready here is meant for power user who would want to test back compatibility or attempt some roll-backs in case bugs are found, and for readers who want to learn about the release notes of each new FPGA version.

(* "Purple" refers to the official 2025+ release of the K2; "Black" refers to the first run of K2B boards sent out to the original F256K owners in late 2024)

Latest FPGA core files for all platforms

F256Jr2				F256K2
Core	Link	Notes		Core	Link	Notes
6502 MMU	08-Jan-2025	OPL3 added		6502 MMU	Black*: 02-Feb-2025 Purple*: n/a	fix Onboard Access to a SPI Flash LCD Splash Screen
65816 Ext	21-Dec-2025	Implementation of the 256Bytes Copy from Flash to RAM before booting.		65816 Ext	Black*: 07-Jan-2025 Purple*: n/a	Updated access to WS6100 UART for the VS1053B
65816 Ext 2x	Buy Here	2x CPU speed layer of 16 bit colored text hardware line drawing 64 more sprites.		65816 Ext 2x	Buy Here	2x CPU speed layer of 16 bit colored text hardware line drawing 64 more sprites.
6809	15-Jun-2025	WIFI Speed and Interface (added TX_Empty & RX_Empty Flag)		6809	N/A yet	N/A yet
F256Jr				F256K
Core	Link	Notes		Core	Link	Notes
6502 MMU	26-Jan-2025	fixes Overlay FONT on top of graphic with Background Color Enabled		6502 MMU	26-Jan-2025	fixes Overlay FONT on top of graphic with Background Color Enabled
65816 Ext 2x	16-Jun-2025	CPU runs at 2x speed at 12 MHz MUST use a 65816 cpu chip, will not work with the 6502		65816 Ext 2x	18-Jun-2025	CPU runs at 2x speed at 12 MHz MUST use a 65816 cpu chip, will not work with the 6502

Previous FPGA core files for all platforms

Use these for testing out older softwares and snooping around for persistant issues.

Previous F256Jr2 Cores
Core	Link	Notes
6809	13-Jun-2025	Move the FG & BG Text LUT to: $18_3800        $18_383F            TEXT_LUT_FG $18_3840        $18_387F            TEXT_LUT_BG
6809	11-Jun-2025	big Wishlist full access to write back the onboard flash
6809	17-Jan-2025	Fix for the manual Reset Fix for the readback of Multiplication Values Endianess Changes to: Line/Pixel Position

Previous F256K2 Cores
Core	Link	Notes
6502 MMU	Black*: 08-Jan-2025 Purple*: n/a	OPL3 implemented
6502 MMU	Black*: 07-Jan-2025 Purple*: n/a	Instantiation of the UART for the VS1053B @ $DDB0
6809	N/A yet	N/A yet

Previous F256Jr Cores
Core	Link	Notes
6502 MMU	23-Dec-2023	Tiles fix; shifted by one towards the left. (0100 = Serial RAM/Flash Select)
6502 MMU	18-Nov-2023	In light of decision to dump the big ticket items and the accessories from the store... Removed the very SPI core introduced yesterday to drive the FNXNET51 module. Removed the DP memory for the MMU and replace it back with simple Registers, which means that when you reset the system, the MMU, Page0 will be reset back to the way it was. However, the caveat is that if you change between RAM to FLASH MMU default value, you need to do a reset, either a debug reset or General Reset because the MMU is now only 32bytes in Size, so, 4 pages of 8 values.
6502 MMU	17-Nov-2023	No Write Allowed when Debug Port writes in the MMU Memory Zone Incorporation of a new SPI Controller to interface with the FNXNET51 module using the NES/SNES MiniDin9 Connector ReSync of the Debug Generated RDY to stop the CPU. (untested)
6502 MMU	various older
6809	n/a	n/a

Previous F256K Cores
Core	Link	Notes
6502 MMU	23-Dec-2023	Tiles fix; shifted by one towards the left.
6502 MMU	09-Dec-2023	Fixes a problem with Interrupt from timer0 that was working on the Jr. Resolves a discrepancy between the F256Jr interrupt block and the F256K.
6502 MMU	19-Nov-2023	Corrects the issue with no-response from command $20 & $21 (not being processed in the early parser). The Jr doesn't have the issue.
6502 MMU	various older
6809	N/A yet	N/A yet

---old version will be kept at the bottom for a while in case errors are found above---

FPGA Upgrade Guide

How to Upgrade the F256K FPGA (and F256Jr)

Note that the below Video Guide applies to both the F256K & F256Jr, despite it just being titled F256K.

You will need to download Quartus Prime Lite 18.1 Edition, since you are going to target a EP4CE15 FPGA (Cyclone 4).

Do not update to the latest version of Quartus Prime Lite, as the latest version doesn’t support that family of FPGA anymore and the software is very big.

Also, one might want to download only the "Intel® Quartus® Prime Programmer and Tools" as opposed to download the whole software by clicking on "Additional Software"

Intel Quartus Prime Lite Edition 18.1 for Windows

Intel Quartus Prime Lite Edition 18.1 for Linux

How to Upgrade the FPGA for the F256K2

It is possible that there will be more graceful methods in the future, but for now, the easiest is to pop off the uSD card found on the left side of the board marked "uSD Card / FPGA Load" and to replace the .bin files inside the directory of the root of that uSD card, using a modern computer.

This will of course imply that you open up your case. There is a guide on how to do so for the original F256K enclosure. Perhaps the F256K2 enclosure will be similar.

For those unfamiliar with the process of removing the uSD card from these slide-operation holders here is the process:

1) very gently press down on the middle metal locking slider that goes across on top of the uSD card and slide it towards the left.

2) the uSD card and its locking slider will now open up by rotating towards the left with a hinge on the left side

Inside the root of this uSD card, there are four folders marked as CNTX# where # is a number from 1 to 4. Simply replace the .bin file therein to update any one given core. You may completely ignore .prm files since they do not affect the F256K2.

Folder	FPGA Core description	CPU in the FPGA
CNTX1	F256 Classic mode with a memory management unit (MMU), where the CPU sees 64k at once	65816 acting as 6502
CNTX2	F256 Extended mode with a flat memory map all accessible at once	65816
CNTX3	F256 with the 6809 core	6809
CNTX4	??? To be determined later

How to Upgrade the FPGA for the F256Jr. the 2nd

Go look at this guide here in the wiki.

Suggested USB Blaster (K and Jr. only)

Earth People Technology [1] [2]

Terasic USB Blaster (low cost version) [3] [4]

Chinese Knockoff (please avoid if possible)

Open Source blaster software (K and Jr. only)

For those who are struggling to program the FPGA with Linux or Apple, Stef found this great tool:

https://github.com/trabucayre/openFPGALoader/releases

Backup of the old tables

Current F256K2 Release

(* "Purple" refers to the official 2025+ release of the K2; "Black" refers to the first run of K2B boards sent out to the original F256K owners in late 2024)

Series	Core	Version	Code	Date	Download (Purple*)	Download (Black*)	Release Notes
F256K2	6502 MMU	?	?	02-Feb-2025		CFP95600C.bin	This fix a small issue with the Onboard Access to a SPI Flash (Splash Screen data). So, for those who will soon receive their official Enclosure, this is a load that you will want to get the LCD Splash Screen going.
F256K2	65816 Extended	?	?	07-Jan-2025		CFP95616E.bin	Updated the code to access the WS6100 - Been verified by @gadget Instantiation of the UART for the VS1053B (it is exactly like the SAM2695 UART, same code) (to be tested)
F256K2	65816 Extended 2x	?	?	summer 2025	N/A	N/A	This special core must be purchased: https://c256foenix.com/product-category/gen2-core/?v=5435c69ed3bc It gives 2x CPU speed, adds a layer of 16 bit colored text, hardware line drawing, 64 more sprites.
F256K2	6809					not yet

Previous F256K2 Releases

Series	Core	Version	Code	Date	Download (Purple*)	Download (Black*)	Release Notes
F256K2	6502 MMU	?	01390005 B3	08-Jan-2025		CFP95600C.bin	OPL3 implemented
F256K2	6502 MMU	?	01390005 (B2?)	07-Jan-2025		CFP95600C.bin	Instantiation of the UART for the VS1053B (it is exactly like the SAM2695 UART, same code) The overall Load will need to be tested but the new thing is the UART for the VS1053B that is located @ $DDB0

F256Jr2 FPGA Releases

Current F256Jr2 Release

Series	Core	Version	Code	Date	Download	Release Notes
F256Jr2	6502 MMU	?	?	08-Jan-2025	F256Jr2_MMU_Jan8th_2025_OPL3.mcs	OPL3 implemented
F256Jr2	65816 Extended	?	?	21-Dec-2024	F256Jr2_Ext16_Dec21st_2024.mcs	updates the RevA1A (I think it is going to work for A0A, if there is an issue it would be with the System Serial Port). Changes - Implementation of the 256Bytes Copy from Flash to RAM before booting.
F256Jr2	6809	RC014	?	17-Jan-2025	F256Jr2_FNX6809_Jan17th_RC0014_0002.mcs	Fix for the manual Reset Fix for the readback of Multiplication Values Endianess Changes to: Line/Pixel Position

Previous F256Jr2 Releases

Series	Core	Version	Code	Date	Download	Release Notes

F256K FPGA Releases

Current F256K Release

Series	Core	Version	Code	Date	Download	Release Notes
F256K	6502 MMU	Release Candidate 16	00160000 B0	26-Jan-2025	F256Kc_WBh_Jan26th_2025_RC16_0001.jic	This is the Fix for FONT overlay with Graphic background when BG is zero
F256K	65816 Extended 2x	Release Candidate 01	?	18-Jun-2025	F256Kc_WBh_Jun18th_2025_RC0100_0000_DualSpeed_CPU.jic	CPU runs at 2x speed at 12 MHz You MUST use a 65816 cpu chip, this will not work with the 6502 installed in the CPU socket

Previous F256K Releases

Series	Core	Version	Code	Date	Download	Release Notes
F256K	6502 MMU	Release Candidate 14	00140000 B0	23-Dec-2023	github: F256K_WBh_Dec23rd_RevB0x_RC14_0000.jic discord: F256K_WBh_Dec23rd_RevB0x_RC14_0000.jic	Fixes a problem with the tiles; needed to be shifted by one towards the left.
F256K	6502 MMU	Release Candidate 13	00130000 B0	09-Dec-2023	github: F256K_WBh_Dec9th_RevB0x_RC13_0000.jic discord: F256K_WBh_Dec9th_RevB0x_RC13_0000.jic	Fixes a problem with Interrupt from timer0 that was working on the Jr. Resolves a discrepancy between the F256Jr interrupt block and the F256K.
F256K	6502 MMU	Release Candidate 12	00120011 B0	19-Nov-2023	github: F256K_WBh_Nov19th_RevB0x_RC12_0011.jic discord: F256K_WBh_Nov19th_RevB0x_RC12_0011.jic	Corrects the issue with no-response from command $20 & $21 (not being processed in the early parser). The Jr doesn't have the issue.
F256K	6502 MMU	various older		various	See here for a dump of older releases: github repo

F256Jr FPGA Releases

Current F256Jr Release

Series	Core	Version	Code	Date	Download	Release Notes
F256Jr	6502 MMU	Release Candidate 20	00200000 B0	26-Jan-2025	F256M_Wbh_Jan26th_2025_RC20_0100.jic	fixes the Overlay FONT on top of graphic with Background Color Enabled
F256Jr	65816 Extended	Release Candidate 01	?	16-Jun-2025	F256M_Wbh_Jun17th_2025_RC0100_0001.jic	CPU runs at 2x speed at 12 MHz You MUST use a 65816 cpu chip, this will not work with the 6502 installed in the CPU socket

Previous F256Jr Releases

Series	Core	Version	Code	Date	Download	Release Notes
F256Jr	6502 MMU	Release Candidate 18	00180100 B0	23-Dec-2023	github: F256M_Wbh_Dec23rd_2023_RC18_0100.jic discord: F256M_Wbh_Dec23rd_2023_RC18_0100.jic	Fixes a problem with the tiles; needed to be shifted by one towards the left. (0100 = Serial RAM/Flash Select)
F256Jr	6502 MMU	Release Candidate 17	?	18-Nov-2023	github:F256M_Wbh_Nov18th_2023_RC17_0100.jic discord: F256M_Wbh_Nov18th_2023_RC17_0100.jic	In light of decision to dump the big ticket items and the accessories from the store... Removed the very SPI core introduced yesterday to drive the FNXNET51 module. Removed the DP memory for the MMU and replace it back with simple Registers, which means that when you reset the system, the MMU, Page0 will be reset back to the way it was. However, the caveat is that if you change between RAM to FLASH MMU default value, you need to do a reset, either a debug reset or General Reset because the MMU is now only 32bytes in Size, so, 4 pages of 8 values.
F256Jr	6502 MMU	Release Candidate 16	?	17-Nov-2023	github: F256M_WBh_Nov17th_2023_RC16_0111.jic discord:F256M_WBh_Nov17th_2023_RC16_0111.jic	No Write Allowed when Debug Port writes in the MMU Memory Zone Incorporation of a new SPI Controller to interface with the FNXNET51 module using the NES/SNES MiniDin9 Connector ReSync of the Debug Generated RDY to stop the CPU. (untested)
F256Jr	6502 MMU	various older		various	See here for a dump of older releases: github repo