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More detailed information is found in the [[Manuals]].
More detailed information is found in the [[Manuals]].


=== Notes ===
== Notes ==
'''SRAM Address''': The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, Core2x has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 24-bit CPU-visible addresses.
<span id="SRAM Address>'''SRAM Address'''</span>: Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, Core2x has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 24-bit CPU-visible addresses.


'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.
'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.


'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.
<span id="BGR">'''BGR'''</span>: A 3-byte color entry in Blue, Green, Red order.
 
<span id="BGRx">'''BGRx'''</span>: A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.


== IO Page 0 ==
== IO Page 0 ==
====== $C000 Gamma Lookup ======
{| class="wikitable"
{| class="wikitable"
|+Gamma Lookup
!MMU
!MMU
!Flat
!Flat
Line 19: Line 22:
|$C000 - $C0FF
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|$F0:0000 - $F0:00FF
|RW
|
|
|
|Blue gamma conversion table
|Blue conversion table
|-
|-
|$C400 - $C4FF
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|$F0:0400 - $F0:04FF
|RW
|
|
|
|Green gamma conversion table
|Green conversion table
|-
|-
|$C800 - $C8FF
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|$F0:0800 - $F0:08FF
|RW
|
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.
====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|
|Red conversion table
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
|}
This is currently mirrored 4 times in $CC00 - $CFFF.


=== Master Control Registers ($D0xx, $F0:10xx) ===
===== $D000: VICKY Config =====
 
====== $D000: Master Control Registers ======
{| class="wikitable"
{| class="wikitable"
|+Master Control
!MMU
!MMU
!Flat
!Flat
Line 101: Line 123:


'''FON_SET''': Chooses font set 0 or 1
'''FON_SET''': Chooses font set 0 or 1
====== $D002: Layers ======
{| class="wikitable"
{| class="wikitable"
|+Layer Configuration
!MMU
!MMU
!Flat
!Flat
!R/W
!R/W
!Name
!7
!7
!6
!6
Line 116: Line 140:
|-
|-
|$D002
|$D002
|$F0:1002
|RW
|
|
|RW
|—
|—
| colspan="3" |Layer 1
| colspan="3" |Layer 1
Line 124: Line 149:
|-
|-
|$D003
|$D003
|$F0:1003
|RW
|
|
|RW
|—
|—
|—
|—
Line 132: Line 158:
|—
|—
| colspan="3" |Layer 2
| colspan="3" |Layer 2
|}
There are 6 configurable graphics maps that can be placed into any of the 3 visible layers. Layer 0 is the front graphics layer.
{| class="wikitable"
|+Layer Codes
!Code
!Graphics Map
|-
|-
|0
|Bitmap 0
|-
|1
|Bitmap 1
|-
|2
|Bitmap 2
|-
|
|
|
|-
|
|4
|
|Tilemap 0
|Values
|-
| colspan="8" |0-2: Bitmap 0-2
|5
4-6: Tilemap 0-2
|Tilemap 1
|-
|6
|Tilemap 2
|}
|}
====== $D004: Border ======
{| class="wikitable"
{| class="wikitable"
|+Border
!MMU
!MMU
!Flat
!Flat
Line 176: Line 183:
|-
|-
|$D004
|$D004
|
|$F0:1004
|RW
|RW
|BRDR_CTRL
|BRDR_CTRL
Line 187: Line 194:
|-
|-
|$D005
|$D005
|
|$F0:1005
|RW
|RW
|BRDR_BLUE
|BRDR_BLUE
Line 193: Line 200:
|-
|-
|$D006
|$D006
|
|$F0:1006
|RW
|RW
|BRDR_GREEN
|BRDR_GREEN
Line 199: Line 206:
|-
|-
|$D007
|$D007
|
|$F0:1007
|RW
|RW
|BRDR_RED
|BRDR_RED
Line 205: Line 212:
|-
|-
|$D008
|$D008
|
|$F0:1008
|RW
|RW
|BRDR_WIDTH
|BRDR_WIDTH
Line 214: Line 221:
|-
|-
|$D009
|$D009
|
|$F0:1009
|RW
|RW
|BRDR_HEIGHT
|BRDR_HEIGHT
Line 222: Line 229:
| colspan="5" |SIZE_Y
| colspan="5" |SIZE_Y
|}
|}
====== $D00D: Background ======
{| class="wikitable"
{| class="wikitable"
|+Background Color
!MMU
!MMU
!Flat
!Flat
Line 238: Line 246:
|-
|-
|$D00D
|$D00D
|
|$F0:100D
|RW
|RW
|BGND_BLUE
|BGND_BLUE
Line 244: Line 252:
|-
|-
|$D00E
|$D00E
|
|$F0:100E
|RW
|RW
|BGND_GREEN
|BGND_GREEN
Line 250: Line 258:
|-
|-
|$D00F
|$D00F
|
|$F0:100F
|RW
|RW
|BGND_RED
|BGND_RED
| colspan="8" |Background color Red component
| colspan="8" |Background color Red component
|}
|}
====== $D010: Text Cursor ======
{| class="wikitable"
{| class="wikitable"
|+Text Cursor
!MMU
!MMU
!Flat
!Flat
Line 271: Line 280:
|-
|-
|$D010
|$D010
|
|$F0:1010
|RW
|RW
|CCR
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|
|
|
|
|RATE
|FLASH_DIS
| colspan="8" |0: 1 second
| colspan="2" |RATE
1: 1/2 second
|ENABLE
2: 1/4 second
3: 1/8 second
|-
|-
|$D012
|$D012
|
|$F0:1012
|RW
|RW
|CCH
|CCH
| colspan="8" |Cursor character code
| colspan="8" |Cursor character code
|-
|-
|$D014 - $D015
|$D014
|
|$F0:1014
|RW
|RW
|CURX
|CURX
| colspan="8" |Cursor X position (16-bit)
| colspan="8" |Cursor X position (16-bit)
|-
|-
|$D016 - $D017
|$D016
|
|$F0:1016
|RW
|RW
|CURY
|CURY
| colspan="8" |Cursor Y position (16-bit)
| colspan="8" |Cursor Y position (16-bit)
|}
|}
====== $D018: Raster ======
{| class="wikitable"
{| class="wikitable"
|+Cursor Flash Rate
!Value
!Rate
|-
|0
|1 second
|-
|1
|1/2 second
|-
|2
|1/4 second
|-
|3
|1/8 second
|}
{| class="wikitable"
|+Raster
!MMU
!MMU
!Flat
!Flat
Line 332: Line 334:
!0
!0
|-
|-
|$D018 - $D019
|$D018
|
|$F0:1018
|R
|R
|RAST_COL
|RAST_COL
| colspan="8" |Raster current column (12-bit)
| colspan="8" |Raster current column (12-bit)
|-
|-
|$D01A - $D01B
|$D01A
|
|$F0:101A
|R
|R
|RAST_ROW
|RAST_ROW
Line 345: Line 347:
|-
|-
|$D018
|$D018
|
|$F0:1018
|W
|W
|LINT_CTRL
|LINT_CTRL
|
|—
|
|—
|
|—
|
|—
|
|—
|
|—
|
|—
|ENABLE
|ENABLE
|-
|-
|$D019 - $D01A
|$D019
|
|$F0:1019
|W
|W
|LINT_L
|LINT_L
Line 364: Line 366:
|}
|}


=== Bitmap Control Registers ($D1xx, $F0:11xx) ===
===== $D100: Bitmaps =====
{| class="wikitable"
{| class="wikitable"
|+Bitmaps
!MMU
!MMU
!Flat
!Flat
Line 381: Line 382:
|-
|-
|$D100
|$D100
|$F0:1100
|
|
|
|RW
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
|
|
| colspan="8" |Bitmap 2
|-
|
|
| +0
|RW
|
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
| colspan="2" |CLUT
|ENABLE
|ENABLE
|-
|-
|$D101 - $D103
|
|
| +1
|RW
|RW
|
|
| colspan="8" |SRAM Address of bitmap 0 pixels (24-bit)
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}
 
===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$D108
|$D200
|$F0:1200
|
|
|RW
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
|
|
|
| colspan="8" |Tilemap 2
| colspan="2" |CLUT
|ENABLE
|-
|-
|$D109 - $D10B
|
|
|RW
| +$00
|W
|
|
| colspan="8" |SRAM Address of bitmap 1 pixels (24-bit)
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|-
|$D110
|
|
|RW
| +$01
|W
|
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit)
|-
|
|
| +$04
|W
|
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
|
| +$06
|W
|
|
|
| colspan="8" |MAP_SIZE_Y (8-bit)
| colspan="2" |CLUT
|ENABLE
|-
|-
|$D111 - $D103
|
|
|RW
| +$08
|W
|
|
| colspan="8" |SRAM Address of bitmap 2 pixels (24-bit)
| colspan="4" |X[3:0]
| colspan="4" |SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" |Y[3:0]
| colspan="4" |SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Y[7:4]
|}
|}


=== Tilemap Control Registers ($D2xx, $F0:12xx) ===
====== $D280: Tilesets ======
{| class="wikitable"
{| class="wikitable"
!MMU
!MMU
Line 450: Line 530:
!0
!0
|-
|-
|$D200
|$D280
|$F0:1280
|
|
|
|
|
| colspan="8" |Tileset 0
| colspan="8" |Tilemap 0
|-
|-
|$D20C
|$D284
|$F0:1284
|
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
|
|
| colspan="8" |Tilemap 1
| colspan="8" |Tileset 2
|-
|-
|$D218
|$D28C
|$F0:128C
|
|
|
|
|
| colspan="8" |Tileset 3
| colspan="8" |Tilemap 2
|}
{| class="wikitable"
|+Tilemap
!Offset
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$00
|$D290
|W
|$F0:1290
|
|
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
|
|
|TILE_SIZE_8
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
|
|
|
| colspan="8" |Tileset 6
|ENABLE
|-
|-
|$01 - $03
|$D29C
|W
|$F0:129C
|
|
|
| colspan="8" |SRAM Address of tile map entries (24-bit)
| colspan="8" |Tileset 7
|-
|-
|$04
|W
|
|
| colspan="8" |MAP_SIZE_X (8-bit)
| +0
|-
|$06
|W
|W
|
|
| colspan="8" |MAP_SIZE_Y (8-bit)
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|-
|$08
|W
|
|
| colspan="4" |X[3:0]
| +3
| colspan="4" |SSX
|-
|$09
|W
|W
|
|
|—
|—
|—
|—
| colspan="6" |X[9:4]
|-
|$0A
|W
|
| colspan="4" |Y[3:0]
| colspan="4" |SSY
|-
|$0B
|W
|
|—
|—
|—
|SQUARE
|—
|—
|—
|—
|—
|—
| colspan="4" |Y[7:4]
|}
|}
===== $D400: Sound =====
====== $D400: SID chips ======
{| class="wikitable"
{| class="wikitable"
|+Tilesets
!MMU
!MMU
!Flat
!Flat
Line 552: Line 615:
!0
!0
|-
|-
|$D280 - $D283
|$D400
|$F0:1400
|
|
|
|
|
| colspan="8" |Left SID
| colspan="8" |Tileset 0
|-
|-
|$D284 - $D287
|$D500
|$F0:1500
|
|
|
|
| colspan="8" |Right SID
|-
|
|
| colspan="8" |Tileset 1
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|-
|$D288 - $D28B
|
|
| +$02
|W
|
|
|
| colspan="8" |Pulse width (12-bit)
| colspan="8" |Tileset 2
|-
|-
|$D28C - $D28F
|
|
| +$04
|W
|
|
|
|NOISE
| colspan="8" |Tileset 3
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|-
|$D290 - $D293
|
|
| +$05
|W
|
|
|
| colspan="4" |ATTACK
| colspan="8" |Tileset 4
| colspan="4" |DELAY
|-
|-
|$D294 - $D298
|
|
| +$06
|W
|
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
|
| colspan="8" |Tileset 5
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|-
|$D298 - $D29B
|
|
| +$09
|W
|
|
|
| colspan="8" |Pulse width (12-bit)
| colspan="8" |Tileset 6
|-
|-
|$D29C - $D29F
|
|
| +$0B
|W
|
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
|
| colspan="8" |Tileset 7
| +$0C
|}
{| class="wikitable"
|+Tileset
!Offset
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0 - 2
|W
|W
|
|
| colspan="8" |SRAM Address of tile pixels (24-bit)
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|-
|3
|
| +$0D
|W
|W
|
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
|
| +$10
|W
|
|
| colspan="8" |Pulse width (12-bit)
|-
|
|
|SQUARE
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
|
| +$14
|W
|
|
|}
| colspan="4" |SUSTAIN
{| class="wikitable"
| colspan="4" |RELEASE
|+
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$D400
|
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
|
| +$16
|W
|
|
| colspan="8" |Left SID
| colspan="8" |FC[10:3]
|-
|-
|$D500
|
|
| +$17
|W
|
|
|
| colspan="4" |RESONANCE
| colspan="8" |Right SID
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}
|}
====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
{| class="wikitable"
|+SID Registers
!MMU
!Offset
!Flat
!R/W
!R/W
!Name
!Name
Line 672: Line 798:
!0
!0
|-
|-
| +$00 - $01
|$D580
|$F0:1580
|W
|W
|Voice 1
|
| colspan="8" |Frequency (16-bit)
| colspan="8" |Address registers for ports $000 - $0FF
|-
|-
| +$02 - $03
|$D581
|$F0:1581
|W
|W
|
|
| colspan="8" |Pulse width (12-bit)
| colspan="8" |Data registers for all ports
|-
|-
| +$04
|$D582
|$F0:1582
|W
|W
|
|
|NOISE
| colspan="8" |Address register for ports $100 - $1FF
|PULSE
|}
|SAW
 
|TRI
====== $D600: PSGs ======
|TEST
Main page: [[Use the PSG]]
|RING
{| class="wikitable"
|SYNC
!MMU
|GATE
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
| +$05
|$D600
|W
|$F0:1600
|
|
| colspan="4" |ATTACK
|DELAY
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
|
|
| colspan="8" |PSG Left + Right
|-
|-
| +$06
|$D610
|W
|$F0:1610
|
|
|
| colspan="4" |SUSTAIN
| colspan="8" |PSG Right
| colspan="4" |RELEASE
|}
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
 
====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
| +$07 - $08
|$D620
|$F0:1620
|W
|W
|Voice 2
|
| colspan="8" |Frequency (16-bit)
| colspan="8" |DATA[7:0]
|-
|-
| +$09 - $0A
|$D621
|$F0:1621
|W
|W
|
|
| colspan="8" |Pulse width (12-bit)
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|-
| +$0B
|
|
|W
|W
|
|
|NOISE
|—
|PULSE
|—
|SAW
|—
|TRI
|—
|TEST
|—
|RING
|—
|SYNC
|—
|GATE
|START
|}
 
===== $D630: System =====
 
====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
| +$0C
|W
|
|
| colspan="4" |ATTACK
|DELAY
|
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|-
| +$0D
|W
|
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
| +$0E - $0F
|W
|W
|Voice 3
|TXR
| colspan="8" |Frequency (16-bit)
| colspan="8" |TX_DATA
|-
|-
| +$10 - $11
|$D631
|W
|$F0:1631
|
|RW
| colspan="8" |Pulse width (12-bit)
|IER
|-
|—
| +$12
|—
|W
|—
|
|—
|NOISE
|STAT
|PULSE
|ERR
|SAW
|TXE
|TRI
|RXA
|TEST
|RING
|SYNC
|GATE
|-
|-
| +$13
|W
|
| colspan="4" |ATTACK
|DELAY
|
|
|
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|-
| +$14
|W
|
|
| colspan="4" |SUSTAIN
|
| colspan="4" |RELEASE
|
|
| colspan="8" |
|-
|-
| +$15
|$D632
|W
|$F0:1632
|Misc
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
|—
|—
| colspan="3" |STATE
|—
|/PENDING
|—
|—
| colspan="3" |FC[2:0]
|-
|-
| +$16
|W
|
|
| colspan="8" |FC[10:3]
|
|-
| +$17
|W
|W
|
|FCR
| colspan="4" |RESONANCE
| colspan="2" |RXT
|EXT
|FIFO64
|FILTV3
|—
|FILTV2
|DMA
|FILTV1
|TXR
|RXR
|FIFOE
|-
|-
| +$18
|$D633
|W
|$F0:1633
|
|RW
|MUTEV3
|LCR
|HIGH
|DLAB
|BAND
|—
|LOW
| colspan="3" |PARITY
| colspan="4" |VOLUME
|STOP
| colspan="2" |DATA
|}
|}
====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
{| class="wikitable"
|+OPL3 Registers (NOT ON F256JR)
!MMU
!MMU
!Flat
!Flat
Line 831: Line 1,022:
!0
!0
|-
|-
|$D580
|$D640
|
|$F0:1640
|W
|RW
|
|PS2_CTRL
| colspan="8" |Address registers for ports $000 - $0FF
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|-
|$D581
|$D641
|
|$F0:1641
|W
|RW
|
|PS2_OUT
| colspan="8" |Data registers for all ports
| colspan="8" |Data to keyboard
|-
|-
|$D582
|$D642
|
|$F0:1642
|W
|R
|
|KBD_IN
| colspan="8" |Address register for ports $100 - $1FF
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}
|}
====== $D650: Timers ======
{| class="wikitable"
{| class="wikitable"
|+PSG Registers
!MMU
!MMU
!Flat
!Flat
Line 864: Line 1,082:
!0
!0
|-
|-
|$D600
|$D650
|
|$F0:1650
|
|W
|
|T0_CTR
| colspan="8" |PSG Left
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|-
|$D608
|
|
|
|
|
|R
| colspan="8" |PSG Left + Right
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|-
|$D610
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
| colspan="8" |PSG Right
|}
Note the stereo separation is controlled with the '''PSG_ST''' flag.
{| class="wikitable"
|+CODEC Registers
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|
|
|W
|
|
| colspan="8" |DATA[7:0]
|-
|$D621
|
|
|W
|
|
| colspan="7" |REGISTER
|DATA[8]
|-
|-
|$D622
|$D658
|
|$F0:1658
|R
|W
|
|T1_CTR
|—
|—
|—
|—
|—
|—
|—
|—
|—
|UP
|—
|LD
|—
|CLR
|BUSY
|EN
|-
|-
|
|
|
|
|W
|R
|
|T1_STAT
|—
|—
|—
|—
Line 935: Line 1,170:
|—
|—
|—
|—
|START
|EQ
|}
{| class="wikitable"
|+UART Registers
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|
|$D659
|
|$F0:1659
|
|RW
| colspan="9" |'''DLAB = 0'''
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|-
|$D630
|$D65C
|
|$F0:165C
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|
|RW
|RW
|IER
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|—
|—
|—
|—
|STAT
|RELD
|ERR
|RECLR
|TXE
|-
|RXA
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
 
====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$D660
|$F0:1660
|
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|
| colspan="9" |'''DLAB = 1'''
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|-
|$D630 - $D631
|$D66C
|$F0:166C
|
|
|RW
|INT_MASK
|DL
| colspan="8" |Per-interrupt flags (24-bit)
| colspan="8" |DIV (16-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|-
|
|
| +0 & $02
|
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
|
| +0 & $04
|
|
| colspan="8" |
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|-
|$D632
|
|
|R
| +0 & $08
|IIR
|
| colspan="2" |FIFO
|INT_PS2_MOUSE
|FIFO64
| colspan="8" |PS/2 mouse event
|—
| colspan="3" |STATE
|/PENDING
|-
|-
|
|
| +0 & $10
|
|
|W
|INT_TIMER_0
|FCR
| colspan="8" |TIMER0 has reached its target value
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|-
|$D633
|
|
|RW
| +0 & $20
|LCR
|
|DLAB
|INT_TIMER_1
|—
| colspan="8" |TIMER1 has reached its target value
| colspan="3" |PARITY
|-
|STOP
|
| colspan="2" |DATA
| +0 & $80
|}
|
{| class="wikitable"
|INT_CARTRIDGE
|+PS/2 Registers
| colspan="8" |Interrupt asserted from cartridge port
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$D640
|
|
|RW
|
|PS2_CTRL
|
|—
|
|—
| colspan="8" |
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|-
|$D641
|
|
|RW
| +1 & $01
|PS2_OUT
|
| colspan="8" |Data to keyboard
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|-
|$D642
|
|
|R
| +1 & $10
|KBD_IN
|
| colspan="8" |Data in from keyboard FIFO
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|-
|$D643
|
|
|R
| +1 & $20
|MS_IN
|
| colspan="8" |Data in from mouse FIFO
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|-
|$D644
|
|
|R
| +1 & $40
|PS2_STAT
|
|K_AK
|INT_VIA1
|K_NK
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|M_AK
|-
|M_NK
|
|—
| +1 & $80
|—
|
|MEMP
|INT_SDC_INS
|KEMP
| colspan="8" |SD Card has been inserted
|}
{| class="wikitable"
|+Timer Registers
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$D650
|
|
|W
|
|T0_CTR
|
|—
|
|—
| colspan="8" |
|—
|—
|UP
|LD
|CLR
|EN
|-
|-
|
|
| +2 & $01
|
|
|R
|IEC_DATA_i
|T0_STAT
| colspan="8" |IEC data in
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|-
|$D651 - $D653
|
|
|RW
| +2 & $02
|T0_VAL
|
| colspan="8" |VAL (24-bit)
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|-
|$D654
|
|
|RW
| +2 & $04
|T0_CMP_CTR
|
|—
|IEC_ATN_i
|—
| colspan="8" |IEC attention in
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655 - $D657
|
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|-
|
|
| +2 & $08
|
|
|
|IEC_SREQ_i
|
| colspan="8" |IEC service request in
|
|}
|
 
|
====== $D670: DIP Switches ======
|
Main page: [[DIP switches]]
|
{| class="wikitable"
|
!MMU
|
!Flat
|
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$D658
|$D670
|$F0:1670
|R
|
|
|W
|GAMMA
|T1_CTR
|USER2
|—
|USER1
|—
|USER0
|—
| colspan="4" |BOOT
|—
|}
|UP
 
|LD
====== $D680: IEC ======
|CLR
{| class="wikitable"
|EN
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|
|$D680
|
|$F0:1680
|R
|R
|T1_STAT
|IEC_I
|—
|SRQ_i
|—
|—
|—
|—
|—
|ATN_i
|—
|—
|—
|—
|—
|CLK_i
|EQ
|DAT_i
|-
|$D659 - $D65B
|
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|-
|$D65C
|$D681
|
|$F0:1681
|RW
|RW
|T1_CMP_CTR
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|—
|—
|—
|CLK_o
|—
|DAT_o
|—
|}
|—
 
|RELD
====== $D690: RTC ======
|RECLR
|-
|$D65D - $D65F
|
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
{| class="wikitable"
{| class="wikitable"
|+RTC Registers
!MMU
!MMU
!Flat
!Flat
Line 1,236: Line 1,432:
|-
|-
|$D690
|$D690
|
|$F0:1690
|RW
|RW
|Seconds
|Seconds
Line 1,244: Line 1,440:
|-
|-
|$D691
|$D691
|
|$F0:1691
|RW
|RW
|Seconds Alarm
|Seconds Alarm
Line 1,252: Line 1,448:
|-
|-
|$D692
|$D692
|
|$F0:1692
|RW
|RW
|Minutes
|Minutes
Line 1,260: Line 1,456:
|-
|-
|$D693
|$D693
|
|$F0:1693
|RW
|RW
|Minutes Alarm
|Minutes Alarm
Line 1,268: Line 1,464:
|-
|-
|$D694
|$D694
|
|$F0:1694
|RW
|RW
|Hours
|Hours
Line 1,277: Line 1,473:
|-
|-
|$D695
|$D695
|
|$F0:1695
|RW
|RW
|Hours Alarm
|Hours Alarm
Line 1,286: Line 1,482:
|-
|-
|$D696
|$D696
|
|$F0:1696
|RW
|RW
|Days
|Days
Line 1,295: Line 1,491:
|-
|-
|$D697
|$D697
|
|$F0:1697
|RW
|RW
|Days Alarm
|Days Alarm
Line 1,304: Line 1,500:
|-
|-
|$D698
|$D698
|
|$F0:1698
|RW
|RW
|Day of Week
|Day of Week
Line 1,315: Line 1,511:
|-
|-
|$D699
|$D699
|
|$F0:1699
|RW
|RW
|Month
|Month
Line 1,325: Line 1,521:
|-
|-
|$D69A
|$D69A
|
|$F0:169A
|RW
|RW
|Year
|Year
Line 1,332: Line 1,528:
|-
|-
|$D69B
|$D69B
|
|$F0:169B
|RW
|RW
|Rates
|Rates
Line 1,340: Line 1,536:
|-
|-
|$D69C
|$D69C
|
|$F0:169C
|RW
|RW
|Enables
|Enables
Line 1,353: Line 1,549:
|-
|-
|$D69D
|$D69D
|
|$F0:169D
|RW
|RW
|Flags
|Flags
Line 1,366: Line 1,562:
|-
|-
|$D69E
|$D69E
|
|$F0:169E
|RW
|RW
|Control
|Control
Line 1,379: Line 1,575:
|-
|-
|$D69F
|$D69F
|
|$F0:169F
|RW
|RW
|Century
|Century
Line 1,385: Line 1,581:
| colspan="4" |1s digit
| colspan="4" |1s digit
|}
|}
====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
{| class="wikitable"
|+Text mode CLUT
!MMU
!MMU
!Flat
!Flat
Line 1,400: Line 1,598:
!0
!0
|-
|-
|$D800 - $D83F
|$D6A0
|
|$F0:16A0
|W
|W
|
|SYS0
| colspan="8" |Text foreground colors (16 × BGRx)
|RESET
|—
|CAP_EN
|BUZZ
|L1
|L0
|SD_L
|PWR_L
|-
|-
|$D840 - $D87F
|
|
|W
|
|
| colspan="8" |Text background colors (16 × BGRx)
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_L
|PWR_L
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MN
|L0_MN
|}
|}
====== $D6A7: F256k Series LEDs ======
Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
{| class="wikitable"
|+Integer Math Coprocessor
!MMU
!MMU
!Flat
!Flat
Line 1,427: Line 1,652:
!0
!0
|-
|-
|$DE00 - $DE01
|$D6A7
|$F0:16A7
|W
|
|
|RW
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|-
|$DE00 - $DE02
|$D6AA
|$F0:16AA
|W
|
|
|RW
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|-
|$DE04 - $DE05
|$D6AD
|$F0:16AD
|W
|
|
|RW
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|DIVU_DEN
|}
| colspan="8" |Division Denominator (Unsigned 16-bit)
 
====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|-
|$DE06 - $DE07
|$D6A8
|
|$F0:16A8
|RW
|R
|DIVU_NUM
|PCBID0
| colspan="8" |Division Numerator (Unsigned 16-bit)
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|-
|$DE08 - $DE0B
|$D6A9
|
|$F0:16A9
|RW
|R
|ADD_A
|PCBID1
| colspan="8" |Addition A (Unsigned 32-bit)
| colspan="8" |ASCII character 1: "0"
|-
|-
|$DE0C - $DE0F
|$D6AA
|
|$F0:16AA
|RW
|R
|ADD_B
|CHSV
| colspan="8" |Addition B (Unsigned 32-bit)
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|-
|
|$D6AE
|
|$F0:16AE
|
|R
|
|CHN
| colspan="8" |
| colspan="8" |VICKY number in BCD (16-bit)
|}
 
====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$DE10 - $DE13
|$D6E0
|$F0:16E0
|W
|
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|RW
|MULU
|
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
| colspan="8" |Y (16-bit)
|-
|-
|$DE14 - $DE15
|$D6E6
|$F0:16E6
|W
|
|
|RW
| colspan="8" |PS2_BYTE_0
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|-
|$DE16 - $DE17
|$D6E7
|$F0:16E7
|W
|
|
|RW
| colspan="8" |PS2_BYTE_1
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|-
|$DE18 - $DE1B
|$D6E8
|$F0:16E8
|W
|
|
|RW
| colspan="8" |PS2_BYTE_2
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.


== IO Page 1 ==
====== $D6EB: PCB Information ======
{| class="wikitable"
{| class="wikitable"
|+Text Mode Font Sets
!MMU
!MMU
!Flat
!Flat
!R/W
!R/W
!Name
!Name
!Description
!7
|-
!6
|$C000 - $C7FF
!5
|$F0:2000 - $F0:27FF
!4
|
!3
|
!2
|Font set 0 (256 × 8-byte chars)
!1
|-
!0
|$C800 - $CFFF
|-
|$F0:2800 - $F0:2FFF
|$D6EB
|
|$F0:16EB
|
|R
|Font set 1 (256 × 8-byte chars)
|PCBMA
|}
| colspan="8" |PCB Major Rev (ASCII)
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.
|-
{| class="wikitable"
|$D6EC
|+Graphics CLUTS
|$F0:16EC
!MMU
|R
!Flat
|PCBMI
!R/W
| colspan="8" |PCB Minor Rev (ASCII)
!Name
|-
!Description
|$D6ED
|-
|$F0:16ED
|$D000 - $D3FF
|R
|$F0:3000 - $F0:33FF
|PCBD
|
| colspan="8" |PCB Day (BCD)
|
|-
|Graphics CLUT 0 (256 × BGRx)
|$D6EE
|-
|$F0:16EE
|$D400 - $D7FF
|R
|$F0:3400 - $F0:37FF
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}
 
===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
 
===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}
 
===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}
 
===== $D900: Sprites =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24
 
2: 16×16
 
3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}
 
===== $DB00: Moar system =====
 
====== $DB00: VIAs ======
See: [[Keyboard raw codes]]
 
<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}
 
====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.
 
====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}
 
===== $DDA0: SAM2695 MIDI (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |Tx FIFO Data Count (12-bit)
|}
 
===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
 
===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.
 
===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.
 
== IO Page 1 ==
 
====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.
 
====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|Graphics CLUT 1 (256 × BGRx)
|-
|-
|$D800 - $DBFF
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|$F0:3800 - $F0:3BFF
|RW
|
|
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|Graphics CLUT 2 (256 × BGRx)
|-
|-
|$DC00 - $DFFF
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|$F0:3C00 - $F0:3FFF
|RW
|
|
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|Graphics CLUT 3 (256 × BGRx)
|}
|}
== IO Page 2 ==
== IO Page 2 ==
====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
{| class="wikitable"
|+
!MMU
!MMU
!Flat
!Flat
Line 1,569: Line 2,770:


== IO Page 3 ==
== IO Page 3 ==
====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
{| class="wikitable"
|+
!MMU
!MMU
!Flat
!Flat

Latest revision as of 18:10, 26 October 2025

More detailed information is found in the Manuals.

Notes

SRAM Address: Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, Core2x has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 24-bit CPU-visible addresses.

Model names: Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

BGR: A 3-byte color entry in Blue, Green, Red order.

BGRx: A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

IO Page 0

$C000 Gamma Lookup
MMU Flat R/W Name Description
$C000 - $C0FF $F0:0000 - $F0:00FF RW Blue gamma conversion table
$C400 - $C4FF $F0:0400 - $F0:04FF RW Green gamma conversion table
$C800 - $C8FF $F0:0800 - $F0:08FF RW Red gamma conversion table

Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

$CC00: Mouse Pointer Bitmap

See: Use the PS/2 Mouse

MMU Flat R/W Name Description
$CC00 - $CCFF $F0:0C00 - $F0:0CFF RW Mouse pointer bitmap (16×16 greyscale bytes)

This is currently mirrored 4 times in $CC00 - $CFFF.

$D000: VICKY Config
$D000: Master Control Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D000 $F0:1000 RW MSTR_CTRL_0 — GAMMA SPRITE TILE BITMAP GRAPH OVRLY TEXT
$D001 $F0:1001 RW MSTR_CTRL_1 — — FON_SET FON_OVLY MON_SLP DBL_Y DBL_X CLK_70

TEXT: Enable text layer

OVRLY: Overlay text on graphics, by making text background transparent. See FON_OVLY

GRAPH: Enable graphics layers (tile, sprites, bitmaps)

BITMAP: Enable bitmap layers (if GRAPH is also set)

TILE: Enable tile layers (if GRAPH is also set)

SPRITE: Enable sprite layers (if GRAPH is also set)

GAMMA: Enable gamma correction

CLK_70: Enable 400p70, else 480p60

DBL_X, DBL_Y: Double text mode character width & height

MON_SLP: Turn off monitor SYNC, putting it into sleep mode

FON_OVLY: Only BG color 0 is transparent in OVRLY mode. Else, all BG colors are transparent.

FON_SET: Chooses font set 0 or 1

$D002: Layers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D002 $F0:1002 RW — Layer 1 — Layer 0
$D003 $F0:1003 RW — — — — — Layer 2
Values 0-2: Bitmap 0-2

4-6: Tilemap 0-2

$D004: Border
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D004 $F0:1004 RW BRDR_CTRL — SCROLL_X — — — ENABLE
$D005 $F0:1005 RW BRDR_BLUE Border color Blue component
$D006 $F0:1006 RW BRDR_GREEN Border color Green component
$D007 $F0:1007 RW BRDR_RED Border color Red component
$D008 $F0:1008 RW BRDR_WIDTH — — — SIZE_X
$D009 $F0:1009 RW BRDR_HEIGHT — — — SIZE_Y
$D00D: Background
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D00D $F0:100D RW BGND_BLUE Background color Blue component
$D00E $F0:100E RW BGND_GREEN Background color Green component
$D00F $F0:100F RW BGND_RED Background color Red component
$D010: Text Cursor
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D010 $F0:1010 RW CCR — — — — FLASH_DIS RATE ENABLE
RATE 0: 1 second

1: 1/2 second 2: 1/4 second 3: 1/8 second

$D012 $F0:1012 RW CCH Cursor character code
$D014 $F0:1014 RW CURX Cursor X position (16-bit)
$D016 $F0:1016 RW CURY Cursor Y position (16-bit)
$D018: Raster
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D018 $F0:1018 R RAST_COL Raster current column (12-bit)
$D01A $F0:101A R RAST_ROW Raster current row (12-bit)
$D018 $F0:1018 W LINT_CTRL — — — — — — — ENABLE
$D019 $F0:1019 W LINT_L Line interrupt line (12-bit)
$D100: Bitmaps
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D100 $F0:1100 Bitmap 0
$D108 $F0:1108 Bitmap 1
$D110 $F0:1110 Bitmap 2
+0 RW — — — — — CLUT ENABLE
+1 RW SRAM Address of pixels (24-bit)
$D200: Tilemaps
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D200 $F0:1200 Tilemap 0
$D20C $F0:120C Tilemap 1
$D218 $F0:1218 Tilemap 2
+$00 W — — — TILE_SIZE_8 — — — ENABLE
+$01 W SRAM Address of tile map entries (24-bit)
+$04 W MAP_SIZE_X (8-bit)
+$06 W MAP_SIZE_Y (8-bit)
+$08 W X[3:0] SSX
+$09 W — — X[9:4]
+$0A W Y[3:0] SSY
+$0B W — — — — Y[7:4]
$D280: Tilesets
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D280 $F0:1280 Tileset 0
$D284 $F0:1284 Tileset 1
$D288 $F0:1288 Tileset 2
$D28C $F0:128C Tileset 3
$D290 $F0:1290 Tileset 4
$D294 $F0:1294 Tileset 5
$D298 $F0:1298 Tileset 6
$D29C $F0:129C Tileset 7
+0 W SRAM Address of tile pixels (24-bit)
+3 W — — — — SQUARE — — —
$D400: Sound
$D400: SID chips
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D400 $F0:1400 Left SID
$D500 $F0:1500 Right SID
+$00 W Voice 1 Frequency (16-bit)
+$02 W Pulse width (12-bit)
+$04 W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$05 W ATTACK DELAY
+$06 W SUSTAIN RELEASE
+$07 W Voice 2 Frequency (16-bit)
+$09 W Pulse width (12-bit)
+$0B W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$0C W ATTACK DELAY
+$0D W SUSTAIN RELEASE
+$0E W Voice 3 Frequency (16-bit)
+$10 W Pulse width (12-bit)
+$12 W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$13 W ATTACK DELAY
+$14 W SUSTAIN RELEASE
+$15 W Misc — — — — — FC[2:0]
+$16 W FC[10:3]
+$17 W RESONANCE EXT FILTV3 FILTV2 FILTV1
+$18 W MUTEV3 HIGH BAND LOW VOLUME
$D580: OPL3 (NOT on F256Jr!)

Main page: Use the OPL3 YMF262

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D580 $F0:1580 W Address registers for ports $000 - $0FF
$D581 $F0:1581 W Data registers for all ports
$D582 $F0:1582 W Address register for ports $100 - $1FF
$D600: PSGs

Main page: Use the PSG

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D600 $F0:1600 PSG Left
$D608 $F0:1608 PSG Left + Right
$D610 $F0:1610 PSG Right

Stereo separation is enabled with the PSG_ST flag. By default, both PSGs go to both speakers.

$D620: CODEC

Main page: Use the CODEC

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D620 $F0:1620 W DATA[7:0]
$D621 $F0:1621 W REGISTER DATA[8]
$D622 $F0:1622 R — — — — — — — BUSY
W — — — — — — — START
$D630: System
$D630: UART
MMU Flat R/W Name 7 6 5 4 3 2 1 0
DLAB = 0
$D630 $F0:1630 R RXD RX_DATA
W TXR TX_DATA
$D631 $F0:1631 RW IER — — — — STAT ERR TXE RXA
DLAB = 1
$D630 $F0:1630 RW DL DIV (16-bit)
$D632 $F0:1632 R IIR FIFO FIFO64 — STATE /PENDING
W FCR RXT FIFO64 — DMA TXR RXR FIFOE
$D633 $F0:1633 RW LCR DLAB — PARITY STOP DATA
$D640: PS/2

See: Use the PS/2 Mouse

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D640 $F0:1640 RW PS2_CTRL — — MCLR KCLR M_WR — K_WR —
$D641 $F0:1641 RW PS2_OUT Data to keyboard
$D642 $F0:1642 R KBD_IN Data in from keyboard FIFO
$D643 $F0:1643 R MS_IN Data in from mouse FIFO
$D644 $F0:1644 R PS2_STAT K_AK K_NK M_AK M_NK — — MEMP KEMP
$D650: Timers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D650 $F0:1650 W T0_CTR — — — — UP LD CLR EN
R T0_STAT — — — — — — — EQ
$D651 $F0:1651 RW T0_VAL VAL (24-bit)
$D654 $F0:1654 RW T0_CMP_CTR — — — — — — RELD RECLR
$D655 $F0:1655 RW T0_CMP CMP (24-bit)
$D658 $F0:1658 W T1_CTR — — — — UP LD CLR EN
R T1_STAT — — — — — — — EQ
$D659 $F0:1659 RW T1_VAL VAL (24-bit)
$D65C $F0:165C RW T1_CMP_CTR — — — — — — RELD RECLR
$D65D $F0:165D RW T1_CMP CMP (24-bit)
$D660: Interrupts

Main page: IRQ, IRQ Programming

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D660 $F0:1660 INT_PENDING Per-interrupt flags (24-bit)
$D664 $F0:1664 INT_POLARITY Per-interrupt flags (24-bit)
$D668 $F0:1668 INT_EDGE Per-interrupt flags (24-bit)
$D66C $F0:166C INT_MASK Per-interrupt flags (24-bit)
+0 & $01 INT_VKY_SOF Start of Frame interrupt (beginning of VSYNC)
+0 & $02 INT_VKY_SOL Start of Line interrupt
+0 & $04 INT_PS2_KBD PS/2 keyboard event
+0 & $08 INT_PS2_MOUSE PS/2 mouse event
+0 & $10 INT_TIMER_0 TIMER0 has reached its target value
+0 & $20 INT_TIMER_1 TIMER1 has reached its target value
+0 & $80 INT_CARTRIDGE Interrupt asserted from cartridge port
+1 & $01 INT_UART The UART is ready to receive or send data
+1 & $10 INT_RTC Interrupt from real time clock chip
+1 & $20 INT_VIA0 Event from the joystick VIA chip
+1 & $40 INT_VIA1 Event from the keyboard VIA chip (F256k Series Only!)
+1 & $80 INT_SDC_INS SD Card has been inserted
+2 & $01 IEC_DATA_i IEC data in
+2 & $02 IEC_CLK_i IEC clock in
+2 & $04 IEC_ATN_i IEC attention in
+2 & $08 IEC_SREQ_i IEC service request in
$D670: DIP Switches

Main page: DIP switches

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D670 $F0:1670 R GAMMA USER2 USER1 USER0 BOOT
$D680: IEC
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D680 $F0:1680 R IEC_I SRQ_i — — ATN_i — — CLK_i DAT_i
$D681 $F0:1681 RW IEC_O SRQ_o RST_o NMI_EN ATN_o — — CLK_o DAT_o
$D690: RTC
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D690 $F0:1690 RW Seconds 0 10s digit 1s digit
$D691 $F0:1691 RW Seconds Alarm 0 10s digit 1s digit
$D692 $F0:1692 RW Minutes 0 10s digit 1s digit
$D693 $F0:1693 RW Minutes Alarm 0 10s digit 1s digit
$D694 $F0:1694 RW Hours AM/PM 0 10s digit 1s digit
$D695 $F0:1695 RW Hours Alarm AM/PM 0 10s digit 1s digit
$D696 $F0:1696 RW Days 0 0 10s digit 1s digit
$D697 $F0:1697 RW Days Alarm 0 0 10s digit 1s digit
$D698 $F0:1698 RW Day of Week 0 0 0 0 0 1s digit
$D699 $F0:1699 RW Month 0 0 0 10s digit 1s digit
$D69A $F0:169A RW Year 10s digit 1s digit
$D69B $F0:169B RW Rates 0 WD RS
$D69C $F0:169C RW Enables 0 0 0 0 AIE PIE PWRIE ABE
$D69D $F0:169D RW Flags 0 0 0 0 AF PF PWRF BVF
$D69E $F0:169E RW Control 0 0 0 0 UTI STOP 12/24 DSE
$D69F $F0:169F RW Century 10s digit 1s digit
$D6A0: System Control Registers

Main page: Use the LEDs

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6A0 $F0:16A0 W SYS0 RESET — CAP_EN BUZZ L1 L0 SD_L PWR_L
R SYS0 — SD_WP SD_CD BUZZ L1 L0 SD_L PWR_L
$D6A1 $F0:16A1 RW SYS1 L1_RATE L0_RATE SID_ST PSG_ST L1_MN L0_MN
$D6A7: F256k Series LEDs

Main page: Use the LEDs#LED_Color_Registers_on_the_K_and_K2

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6A7 $F0:16A7 W Power LED color (BGR)
$D6AA $F0:16AA W Media LED color (BGR)
$D6AD $F0:16AD W Shift LED color (BGR)
$D6A7: Machine ID and FPGA Core Versions
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6A7 $F0:16A7 R MID — — — Machine ID
$D6A8 $F0:16A8 R PCBID0 ASCII character 0: "B" (See also $D6EB)
$D6A9 $F0:16A9 R PCBID1 ASCII character 1: "0"
$D6AA $F0:16AA R CHSV VICKY sub-version in BCD (16-bit)
$D6AC $F0:16AC R CHV VICKY version in BCD (16-bit)
$D6AE $F0:16AE R CHN VICKY number in BCD (16-bit)
$D6E0: Mouse Pointer Control
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6E0 $F0:16E0 W — — — — — — MODE EN
$D6E2 $F0:16E2 RW X (16-bit)
$D6E4 $F0:16E4 RW Y (16-bit)
$D6E6 $F0:16E6 W PS2_BYTE_0
$D6E7 $F0:16E7 W PS2_BYTE_1
$D6E8 $F0:16E8 W PS2_BYTE_2
$D6EB: PCB Information
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6EB $F0:16EB R PCBMA PCB Major Rev (ASCII)
$D6EC $F0:16EC R PCBMI PCB Minor Rev (ASCII)
$D6ED $F0:16ED R PCBD PCB Day (BCD)
$D6EE $F0:16EE R PCBM PCB Month (BCD)
$D6EF $F0:16EF R PCBY PCB Year (BCD)
$D700: VS1053b (F256 Gen 2 only)

Main page: Use the VS1053b chip

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D700 $F0:1700 SCI Control Control the flow of information
$D701 $F0:1701 SCI Address Select to which VS1053b address to write to
$D702 $F0:1702 SCI Data 1 First byte of data
$D703 $F0:1703 SCI Data 2 Second byte of data
$D704 $F0:1704 FIFO Count 1 First byte of the remaining byte count in the FIFO
$D705 $F0:1705 FIFO Count 2 Second byte of the remaining byte count in the FIFO
$D800: Text Mode CLUT
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D800 - $D83F $F0:1800 - $F0:183F W Text foreground colors (16 × BGRx)
$D840 - $D87F $F0:1840 - $F0:187f W Text background colors (16 × BGRx)
$D880: NES/SNES Gamepads

Main page: Use the SNES/NES controllers

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D880 $F0:1880 R NES_CTRL NES_TRIG DONE — — — MODE — NES_EN
W NES_CTRL NES_TRIG — — — — MODE — NES_EN
$D884 $F0:1884 Pad 0
$D886 $F0:1886 Pad 1
$D888 $F0:1888 Pad 2
$D88A $F0:188A Pad 3
+0 Mode=0 A B SELECT START UP DOWN LEFT RIGHT
+0 Mode=1 B Y SELECT START UP DOWN LEFT RIGHT
+1 Mode=1 — — — — A X L R
$D900: Sprites
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D900 - $DAFF $F0:1900 - $F0:1AFF 64 × 8-byte Sprite Registers
+0 W — SIZE LAYER LUT ENABLE
SIZE 0: 32×32

1: 24×24

2: 16×16

3: 8×8

+1 W SRAM Address of sprite pixels (24-bit)
+4 W X position (16-bit)
+6 W Y position (16-bit)
$DB00: Moar system
$DB00: VIAs

See: Keyboard raw codes

* = F256k series only

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DB00* $F0:1B00* VIA1 Internal Keyboard VIA*
$DC00 $F0:1C00 VIA0 Atari joystick VIA
+0 RW IORB Port B Data
VIA0: Joystick 0, keyboard column 8*

VIA1: Keyboard columns 0-7*

+1 RW IORA Port A Data
VIA0: Joystick 1

VIA1: Keyboard row*

+2 RW DDRB Port B Data Direction Register
+3 RW DDRA Port A Data Direction Register
+4 RW T1C Timer 1 Counter (16-bit)
+6 RW T1L Timer 1 Latch (16-bit)
+8 RW T2C Timer 2 Counter (16-bit)
+A RW SDR Serial Data Registers
+B RW ACR T1_CTRL T2_CTRL SR_CTRL PBL_EN PAL_EN
+C RW PCR CB2_CTRL CB1_CTRL CA1_CTRL CA1_CTRL
+D RW IFR IRQF T1F T2F CB1F CB2F SRF CA1F CA2F
+E RW IER SET T1E T2E CB1E CB2E SRE CA1E CA2E
+F RW IORA2 Port A Data (no handshake)
VIA0 Joystick Bits
7 6 5 4 3 2 1 0
Keyboard column 8* Button 2 Button 1 Button 0 Right Left Down Up
VIA1 Internal Keyboard Matrix*
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VIA0 PB7
PA0 Del Return Left F7 F1 F3 F5 Up Down
PA1 3 W A 4 Z S E LShift
PA2 5 R D 6 C F T X
PA3 7 Y G 8 B H U V
PA4 9 I J 0 M K O N
PA5 - P L Caps . ; [ ,
PA6 = ] ' Home RShift Alt Tab / Right
PA7 1 BS Ctrl 2 Space Foenix Q Run/Stop
$DD00: SD Card Controllers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DD00 $F0:1D00 SD Card 0 (external)
$DD20 $F0:1D20 SD Card 1 (internal)
+0 RW SPI_BUSY — — — — — SPI_CLK CS_EN
+1 RW SPI_DATA

SPI_CLK: 400MHz init clock when set, 12.5MHz standard clock when clear.

$DD40: F256K2 Case LCD Screen

Main page: Use the K2 LCD

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DD40 $F0:1D40 LCD_CMD_CMD Command
$DD41 $F0:1D41 LCD_CMD_DTA Data
$DD42 $F0:1D42 LCD_PIX_LO Green[2:0] Blue
$DD43 $F0:1D43 LCD_PIX_HI Red Green[5:3]
$DDA0: SAM2695 MIDI (F256 Gen 2 only)

Main page: Use the Sam2695 Dream MIDI chip

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DDA0 $F0:1DA0 R MIDI_STATUS TX_EMPTY RX_FULL — — — — — —
$DDA1 $F0:1DA1 RW MIDI_FIFO_DATA_PORT Data
$DDA2 $F0:1DA2 MIDI_RXD_COUNT Rx FIFO Data count (12-bit)
$DDA4 $F0:1DA4 MIDI_TXD_COUNT Tx FIFO Data Count (12-bit)
$DDC0: Optical Keyboard Controller (F256K2 Only)
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DDC0 $F0:1DC0 OPT_KBD_DATA FIFO queue. Each event is two 8-bit reads from here
$DDC1 $F0:1DC1 R OPT_KBD_STATUS MECH — — — — — — FIFO_EMPTY
MECH = No optical keyboard if set
$DDC2 $F0:1DC2 OPT_KB_COUNT Number of events in optical keyboard queue (12-bit)
$DE00: Integer Math Coprocessor
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DE00 $F0:1E00 RW MULU_A Multiplication A (Unsigned 16-bit)
$DE02 $F0:1E02 RW MULU_B Multiplication B (Unsigned 16-bit)
$DE04 $F0:1E04 RW DIVU_DEN Division Denominator (Unsigned 16-bit)
$DE06 $F0:1E06 RW DIVU_NUM Division Numerator (Unsigned 16-bit)
$DE08 $F0:1E08 RW ADD_A Addition A (Unsigned 32-bit)
$DE0C $F0:1E0C RW ADD_B Addition B (Unsigned 32-bit)
$DE10 $F0:1E10 RW MULU Multiplication A×B Result (Unsigned 32-bit)
$DE14 $F0:1E14 RW QUOU Quotient of Num/Den (Unsigned 16-bit)
$DE16 $F0:1E16 RW REMU Remainder of Num/Den (Unsigned 16-bit)
$DE18 $F0:1E18 RW ADD_R Addition A+B Result (Unsigned 32-bit)

Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

$DF00: DMA Controller
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DF00 $F0:1F00 RW START — — — INT_EN FILL 2D ENABLE
$DF01 $F0:1F01 W Fill data byte
$DF04 $F0:1F04 RW Source SRAM Address (24-bit)
$DF08 $F0:1F08 RW Destination SRAM Address (24-bit)
$DF0C $F0:1F0C RW Count (24-bit, not 2D mode)
RW Width (16-bit, 2D mode)
$DF0E $F0:1F0E RW Height (16-bit, 2D mode)
$DF10 $F0:1F10 RW Source stride (16-bit, 2D mode)
$DF12 $F0:1F12 RW Destination stride (16-bit, 2D mode)

DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

IO Page 1

$C000: Text Mode Font Sets
MMU Flat R/W Name Description
$C000 - $C7FF $F0:2000 - $F0:27FF RW Font set 0 (256 × 8-byte chars)
$C800 - $CFFF $F0:2800 - $F0:2FFF RW Font set 1 (256 × 8-byte chars)

Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

$D000: Graphics CLUTs
MMU Flat R/W Name Description
$D000 - $D3FF $F0:3000 - $F0:33FF RW Graphics CLUT 0 (256 × BGRx)
$D400 - $D7FF $F0:3400 - $F0:37FF RW Graphics CLUT 1 (256 × BGRx)
$D800 - $DBFF $F0:3800 - $F0:3BFF RW Graphics CLUT 2 (256 × BGRx)
$DC00 - $DFFF $F0:3C00 - $F0:3FFF RW Graphics CLUT 3 (256 × BGRx)

IO Page 2

$C000: Text Screen Character Matrix
MMU Flat R/W Name Description
$C000 - $DFFF $F0:4000 - $F0:5FFF RW Text screen character matrix

1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.

IO Page 3

$C000: Text Screen Color Matrix
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$C000 - $DFFF $F0:6000 - $F0:7FFF RW Text screen color matrix
FG color (0-15) BG color (0-15)

Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

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