Hardware: Difference between revisions

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(Added Section for the Memory Expansion Slot)
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=== Overview and Comparison ===
== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
|- style="vertical-align:top;"
Line 11: Line 11:
CPU
CPU
|
|
WDC 65C02<br/>
WDC W65C02S<br/>
WDC 65816S<br/>
WDC W65C816S<br/>
FNX 6809<br/>
Foenix FNX6809<br/>
|
|
WDC 65C02<br/>
WDC W65C02S<br/>
WDC 65816S<br/>
WDC W65C816S<br/>
FNX 6809<br/>
Foenix FNX6809<br/>
|- style="vertical-align:top;"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
! scope="col"; style="text-align:left;" |
Line 47: Line 47:
Audio
Audio
|
|
2 x PSG (Sn76489)<br/>
2 x PSG (SN76489)<br/>
2 x SID socket<br/>
2 x SID socket<br/>
|
|
Line 61: Line 61:
1 x PS2 (Mouse / External Keyboard)<br/>
1 x PS2 (Mouse / External Keyboard)<br/>
1 x Commodore syle IEC Port<br/>
1 x Commodore syle IEC Port<br/>
1 x Headphone 3,5<br/>
1 x Headphone 3.5<br/>
1 x RCA Line Out<br/>
1 x RCA Line Out<br/>
2 x Serial Port Pin-Header<br/>
2 x Serial Port Pin-Header<br/>
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2 x Joystick Atari style Pin-Header<br/>
2 x Joystick Atari style Pin-Header<br/>
1 x PIN-Header onboard for SNES/NES Joystick Connector Box<br/>
1 x PIN-Header onboard for SNES/NES Joystick Connector Box<br/>
1 x RAM Expansion Slot (on Top)<br/>
1 x Memory Expansion Slot (on Top)<br/>
1 x JTAG Port for system updates (on bottom)<br/>
1 x JTAG Port for system updates (on bottom)<br/>
1 x Wifi Module ESP32 Feather (internal)<br/>
1 x Wifi Module ESP32 Feather (internal)<br/>
Line 77: Line 77:
1 x PS2 (Mouse / External Keyboard)<br/>
1 x PS2 (Mouse / External Keyboard)<br/>
1 x Commodore syle IEC Port<br/>
1 x Commodore syle IEC Port<br/>
1 x Headphone 3,5<br/>
1 x Headphone 3.5<br/>
1 x RCA Line Out<br/>
1 x RCA Line Out<br/>
1 x Serial Port DB9M / 1 x Serial Pin Header<br/>
1 x Serial Port DB9M / 1 x Serial Pin Header<br/>
Line 85: Line 85:
2 x Joystick Atari style DB9 Connector<br/>
2 x Joystick Atari style DB9 Connector<br/>
1 x Mini-DIN9 for SNES/NES Joystick Connector Box<br/>
1 x Mini-DIN9 for SNES/NES Joystick Connector Box<br/>
1 x RAM Expansion Slot (on Top)<br/>
1 x Memory Expansion Slot (on Top)<br/>
1 x JTAG Port for system updates (on bottom)<br/>
1 x JTAG Port for system updates (on bottom)<br/>
1 x Wifi Module ESP32 Feather (internal)<br/>
1 x Wifi Module ESP32 Feather (internal)<br/>
Line 91: Line 91:
|}
|}


=== Details ===
== Hardware Details ==


===== CPU =====
=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.


The 65C02 can also be replaced with a [[Template:Main2/65816_Processor|65816]] as a drop in replacement.  '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT.  Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''
The 65C02 can also be replaced with a [[Template:Main2/65816_Processor|65816]] as a drop in replacement.  '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT.  Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''


In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).
=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion.  It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Ouput Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.
Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.
The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket. 
As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.
==== Utilising the Expension Slot (for your own purposes) ====
'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!
If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.
As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal.  For the uni-directional Address and Control lines, the DIR input can be hardwired.
As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate. 
==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}


In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).
==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)  
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output

Revision as of 16:28, 31 March 2024

Hardware Overview and Comparison

F256Jr

F256K

CPU

WDC W65C02S
WDC W65C816S
Foenix FNX6809

WDC W65C02S
WDC W65C816S
Foenix FNX6809

RAM

512 KB
Optional 256K RAM expansion module available

512 KB
Optional 256K RAM expansion module available

Flash

512 KB
Optional 256K Flash Modules

512 KB
Optional 256K Flash Modules

Graphic Chip

TinyVicky

TinyVicky

Audio

2 x PSG (SN76489)
2 x SID socket

2 x PSG
2 x SID hardware emulation on board
OPL3
CODEC

Connections

1 x DVI (digital & analog)
1 x PS2 (Mouse / External Keyboard)
1 x Commodore syle IEC Port
1 x Headphone 3.5
1 x RCA Line Out
2 x Serial Port Pin-Header
1 x Mini-USB Debug Port
1 x Power 12V / 2A, 2,5mm Barrel Connector
1 x SD Card Slot
2 x Joystick Atari style Pin-Header
1 x PIN-Header onboard for SNES/NES Joystick Connector Box
1 x Memory Expansion Slot (on Top)
1 x JTAG Port for system updates (on bottom)
1 x Wifi Module ESP32 Feather (internal)
1 x Real Time Clock Battery CR2032 (internal)

1 x DVI (digital & analog)
1 x PS2 (Mouse / External Keyboard)
1 x Commodore syle IEC Port
1 x Headphone 3.5
1 x RCA Line Out
1 x Serial Port DB9M / 1 x Serial Pin Header
1 x Mini-USB Debug Port
1 x Power 12V / 2A, 2,5mm Barrel Connector
1 x SD Card Slot
2 x Joystick Atari style DB9 Connector
1 x Mini-DIN9 for SNES/NES Joystick Connector Box
1 x Memory Expansion Slot (on Top)
1 x JTAG Port for system updates (on bottom)
1 x Wifi Module ESP32 Feather (internal)
1 x Real Time Clock Battery CR2032 (internal)

Hardware Details

CPU

The basic setup of all F256 is the Western Design Center 65C02, a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a 65816 as a drop in replacement. Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on Discord).

Memory Expansion Slot

The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Ouput Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

Utilising the Expension Slot (for your own purposes)

Warning: All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or you risk damage to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Expansion Slot pin-out

Signal

Side B

Side A

Signal

A4

B1

A1

nRST

A3

B2

A2

A5

A2

B3

A3

A6

A1

B4

A4

A7

A0

B5

A5

A8

CS_RAMn

B6

A6

OEn

D0

B7

A7

D7

D1

B8

A8

D6

3V3

B9

A9

GND

GND

B10

A10

3V3

D2

B11

A11

D5

Key Notch

D3

B12

A12

D4

R/Wn

B13

A13

A9

A17

B14

A14

A10

A16

B15

A15

A11

A15

B16

A16

A12

A14

B17

A17

IRQn

A13

B18

A18

PHI2

Expansion Slot - Signal Descriptions

Signal

Description

A0 - A17

Address Bus output (for addressing $100000 - $13FFFF Expansion space)

D0 - D7

Data Bus (bi-directional)

RSTn

Reset output (active low)

CS_RAMn

Chip Select output for Address Range $100000 - $13FFFF (active low)

OEn

Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)

3V3

3.3V Power output from the F256 (intended to power Expansion Interface only - Don't Exceed 500ma)

GND

Digital Ground reference

R/Wn

Read/Write ouput (Read = high / Write = low)

IRQn

Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)

PHI2

Phase 2 - Clock Output

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