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== F256Jr FPGA Releases == === Current F256Jr Release === {| class="wikitable" ! Series !! Version !Code!! Date !! Download !! Release Notes |- | style="white-space:nowrap;"| F256Jr | style="white-space:nowrap;"| Release Candidate 18 |00180100 B0 | style="white-space:nowrap;" | 23-Dec-2023 | style="white-space:nowrap;"| [https://cdn.discordapp.com/attachments/1010352563406770217/1188629310081347584/F256M_Wbh_Dec23rd_2023_RC18_0100.jic?ex=659b384f&is=6588c34f&hm=e38627d1334595c2bae737ba996c398b5d748a979624b79005cb720664453111& F256M_Wbh_Dec23rd_2023_RC18_0100.jic] |Fixes a problem with the tiles; needed to be shifted by one towards the left. (0100 = Serial RAM/Flash Select) |} === Previous F256Jr Releases === {| class="wikitable" ! Series !! Version !Code!! Date !! Download !! Release Notes |- |F256Jr |Release Candidate 17 |? |18-Nov-2023 |[https://cdn.discordapp.com/attachments/1010352563406770217/1175321652859523123/F256M_Wbh_Nov18th_2023_RC17_0100.jic F256M_Wbh_Nov18th_2023_RC17_0100.jic] |In light of decision to dump the big ticket items and the accessories from the store... * Removed the very SPI core introduced yesterday to drive the FNXNET51 module. * Removed the DP memory for the MMU and replace it back with simple Registers, which means that when you reset the system, the MMU, Page0 will be reset back to the way it was. However, the caveat is that if you change between RAM to FLASH MMU default value, you need to do a reset, either a debug reset or General Reset because the MMU is now only 32bytes in Size, so, 4 pages of 8 values. |- | style="white-space:nowrap;"| F256Jr | style="white-space:nowrap;"| Release Candidate 16 |? | style="white-space:nowrap;" | 17-Nov-2023 | style="white-space:nowrap;"| [https://cdn.discordapp.com/attachments/1010352563406770217/1174998797991022632/F256M_WBh_Nov17th_2023_RC16_0111.jic F256M_WBh_Nov17th_2023_RC16_0111.jic] | * No Write Allowed when Debug Port writes in the MMU Memory Zone * Incorporation of a new SPI Controller to interface with the FNXNET51 module using the NES/SNES MiniDin9 Connector * ReSync of the Debug Generated RDY to stop the CPU. (untested) |}
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